gpio: intel_apl: rework driver for pin_mask callback
To avoid confusion, callbacks using ordinal pin numbers is going to be reverted. So the driver has to be re-worked to expose multiple devices so each device has 32 pins. Also fixes #12765 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Anas Nashif
parent
7695a72e3c
commit
f7a42a70f8
10 changed files with 619 additions and 440 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018 Intel Corporation
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* Copyright (c) 2018-2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,21 +12,26 @@
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* both GPIOs and Pinmuxing function. This driver provides
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* the GPIO function.
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*
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* Currently, this driver does not handle pin triggering.
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*
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* Note that since the GPIO controller controls more then 32 pins,
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* the pin_mux of the API does not work anymore.
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* The GPIO controller has 245 pins divided into four sets.
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* Each set has its own MMIO address space. Due to GPIO
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* callback only allowing 32 pins (as a 32-bit mask) at once,
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* each set is further sub-divided into multiple devices.
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* Because of this, shared IRQ must be used.
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*/
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#include <errno.h>
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#include <gpio.h>
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#include <shared_irq.h>
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#include <soc.h>
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#include <sys_io.h>
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#include <misc/__assert.h>
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#include <misc/slist.h>
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#include "gpio_utils.h"
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#define NUM_ISLANDS 4
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#ifndef CONFIG_SHARED_IRQ
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#error "Need CONFIG_SHARED_IRQ!"
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#endif
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#define REG_PAD_BASE_ADDR 0x000C
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@ -85,40 +90,30 @@
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#define PAD_CFG1_IOSSTATE_MASK (0x0F << PAD_CFG1_IOSSTATE_POS)
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#define PAD_CFG1_IOSSTATE_IGNORE (0x0F << PAD_CFG1_IOSSTATE_POS)
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struct apl_gpio_island {
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u32_t reg_base;
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u32_t num_pins;
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};
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struct gpio_intel_apl_config {
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struct apl_gpio_island islands[NUM_ISLANDS];
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u32_t reg_base;
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u8_t pin_offset;
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u8_t num_pins;
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};
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struct gpio_intel_apl_data {
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/* Pad base address for each island */
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u32_t pad_base[NUM_ISLANDS];
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/* Pad base address */
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u32_t pad_base;
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sys_slist_t cb;
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sys_slist_t cb;
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};
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static inline void extract_island_and_pin(u32_t pin, u32_t *island,
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u32_t *raw_pin)
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{
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*island = pin >> APL_GPIO_ISLAND_POS;
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*raw_pin = pin & APL_GPIO_PIN_MASK;
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}
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#ifdef CONFIG_GPIO_INTEL_APL_CHECK_PERMS
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/**
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* @brief Check if host has permission to alter this GPIO pin.
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*
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* @param "struct device *dev" Device struct
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* @param "u32_t island" Island index
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* @param "u32_t raw_pin" Raw GPIO pin
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*
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* @return true if host owns the GPIO pin, false otherwise
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*/
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static bool check_perm(struct device *dev, u32_t island, u32_t raw_pin)
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static bool check_perm(struct device *dev, u32_t raw_pin)
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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@ -128,7 +123,7 @@ static bool check_perm(struct device *dev, u32_t island, u32_t raw_pin)
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/* read the Pad Ownership register related to the pin */
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offset = REG_PAD_OWNER_BASE + ((raw_pin >> 3) << 2);
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val = sys_read32(cfg->islands[island].reg_base + offset);
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val = sys_read32(cfg->reg_base + offset);
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/* get the bits about ownership */
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offset = raw_pin % 8;
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@ -139,8 +134,8 @@ static bool check_perm(struct device *dev, u32_t island, u32_t raw_pin)
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}
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/* Also need to make sure the function of pad is GPIO */
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offset = data->pad_base[island] + (raw_pin << 3);
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val = sys_read32(cfg->islands[island].reg_base + offset);
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offset = data->pad_base + (raw_pin << 3);
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val = sys_read32(cfg->reg_base + offset);
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if (val & PAD_CFG0_PMODE_MASK) {
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/* mode is not zero => not functioning as GPIO */
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return false;
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@ -152,24 +147,31 @@ static bool check_perm(struct device *dev, u32_t island, u32_t raw_pin)
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#define check_perm(...) (1)
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#endif
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static void gpio_intel_apl_isr(void *arg)
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static int gpio_intel_apl_isr(struct device *dev)
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{
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struct device *dev = arg;
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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struct gpio_callback *cb;
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u32_t island, raw_pin, reg;
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struct gpio_callback *cb, *tmp;
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u32_t reg, int_sts, cur_mask, acc_mask;
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SYS_SLIST_FOR_EACH_CONTAINER(&data->cb, cb, node) {
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extract_island_and_pin(cb->pin, &island, &raw_pin);
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reg = cfg->reg_base + REG_GPI_INT_STS_BASE
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+ ((cfg->pin_offset >> 5) << 2);
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int_sts = sys_read32(reg);
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acc_mask = 0;
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reg = cfg->islands[island].reg_base + REG_GPI_INT_STS_BASE;
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if (sys_bitfield_test_and_set_bit(reg, raw_pin)) {
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SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&data->cb, cb, tmp, node) {
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cur_mask = int_sts & cb->pin_mask;
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acc_mask |= cur_mask;
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if (cur_mask) {
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__ASSERT(cb->handler, "No callback handler!");
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cb->handler(dev, cb, cb->pin);
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cb->handler(dev, cb, cur_mask);
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}
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}
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/* clear handled interrupt bits */
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sys_write32(acc_mask, reg);
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return 0;
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}
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static int gpio_intel_apl_config(struct device *dev, int access_op,
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@ -177,13 +179,20 @@ static int gpio_intel_apl_config(struct device *dev, int access_op,
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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u32_t island, raw_pin, reg, cfg0, cfg1, val;
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u32_t raw_pin, reg, cfg0, cfg1, val;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
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/*
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* Pin must be input for interrupt to work.
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* And there is no double-edge trigger according
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* to datasheet.
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*/
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if ((flags & GPIO_INT)
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&& ((flags & GPIO_DIR_OUT)
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|| (flags & GPIO_INT_DOUBLE_EDGE))) {
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return -EINVAL;
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}
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@ -192,21 +201,24 @@ static int gpio_intel_apl_config(struct device *dev, int access_op,
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return -EINVAL;
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}
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extract_island_and_pin(pin, &island, &raw_pin);
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if (pin > cfg->num_pins) {
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return -EINVAL;
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}
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if (!check_perm(dev, island, raw_pin)) {
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raw_pin = cfg->pin_offset + pin;
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if (!check_perm(dev, raw_pin)) {
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return -EPERM;
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}
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/* Set GPIO to trigger legacy interrupt */
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if (flags & GPIO_INT) {
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reg = cfg->islands[island].reg_base + REG_PAD_HOST_SW_OWNER;
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reg = cfg->reg_base + REG_PAD_HOST_SW_OWNER;
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sys_bitfield_set_bit(reg, raw_pin);
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}
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/* read in pad configuration register */
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reg = cfg->islands[island].reg_base
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+ data->pad_base[island] + (raw_pin * 8);
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reg = cfg->reg_base + data->pad_base + (raw_pin * 8);
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cfg0 = sys_read32(reg);
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cfg1 = sys_read32(reg + 4);
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@ -273,20 +285,23 @@ static int gpio_intel_apl_write(struct device *dev, int access_op,
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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u32_t island, raw_pin, reg, val;
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u32_t raw_pin, reg, val;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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extract_island_and_pin(pin, &island, &raw_pin);
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if (pin > cfg->num_pins) {
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return -EINVAL;
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}
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if (!check_perm(dev, island, raw_pin)) {
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raw_pin = cfg->pin_offset + pin;
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if (!check_perm(dev, raw_pin)) {
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return -EPERM;
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}
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reg = cfg->islands[island].reg_base
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+ data->pad_base[island] + (raw_pin * 8);
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reg = cfg->reg_base + data->pad_base + (raw_pin * 8);
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val = sys_read32(reg);
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if (value) {
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@ -305,20 +320,23 @@ static int gpio_intel_apl_read(struct device *dev, int access_op,
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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u32_t island, raw_pin, reg, val;
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u32_t raw_pin, reg, val;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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extract_island_and_pin(pin, &island, &raw_pin);
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if (pin > cfg->num_pins) {
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return -EINVAL;
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}
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if (!check_perm(dev, island, raw_pin)) {
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raw_pin = cfg->pin_offset + pin;
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if (!check_perm(dev, raw_pin)) {
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return -EPERM;
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}
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reg = cfg->islands[island].reg_base
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+ data->pad_base[island] + (raw_pin * 8);
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reg = cfg->reg_base + data->pad_base + (raw_pin * 8);
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val = sys_read32(reg);
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if (!(val & PAD_CFG0_TXDIS)) {
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@ -345,24 +363,28 @@ static int gpio_intel_apl_enable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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u32_t island, raw_pin, reg;
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u32_t raw_pin, reg;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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extract_island_and_pin(pin, &island, &raw_pin);
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if (pin > cfg->num_pins) {
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return -EINVAL;
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}
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if (!check_perm(dev, island, raw_pin)) {
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raw_pin = cfg->pin_offset + pin;
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if (!check_perm(dev, raw_pin)) {
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return -EPERM;
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}
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/* clear (by setting) interrupt status bit */
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reg = cfg->islands[island].reg_base + REG_GPI_INT_STS_BASE;
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reg = cfg->reg_base + REG_GPI_INT_STS_BASE;
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sys_bitfield_set_bit(reg, raw_pin);
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/* enable interrupt bit */
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reg = cfg->islands[island].reg_base + REG_GPI_INT_EN_BASE;
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reg = cfg->reg_base + REG_GPI_INT_EN_BASE;
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sys_bitfield_set_bit(reg, raw_pin);
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return 0;
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@ -372,20 +394,24 @@ static int gpio_intel_apl_disable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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u32_t island, raw_pin, reg;
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u32_t raw_pin, reg;
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if (access_op != GPIO_ACCESS_BY_PIN) {
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return -ENOTSUP;
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}
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extract_island_and_pin(pin, &island, &raw_pin);
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if (pin > cfg->num_pins) {
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return -EINVAL;
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}
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if (!check_perm(dev, island, raw_pin)) {
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raw_pin = cfg->pin_offset + pin;
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if (!check_perm(dev, raw_pin)) {
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return -EPERM;
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}
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/* disable interrupt bit */
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reg = cfg->islands[island].reg_base + REG_GPI_INT_EN_BASE;
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reg = cfg->reg_base + REG_GPI_INT_EN_BASE;
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sys_bitfield_clear_bit(reg, raw_pin);
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return 0;
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@ -406,62 +432,60 @@ int gpio_intel_apl_init(struct device *dev)
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{
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const struct gpio_intel_apl_config *cfg = dev->config->config_info;
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struct gpio_intel_apl_data *data = dev->driver_data;
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int i;
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gpio_intel_apl_irq_config(dev);
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for (i = 0; i < NUM_ISLANDS; i++) {
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data->pad_base[i] = sys_read32(cfg->islands[i].reg_base
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+ REG_PAD_BASE_ADDR);
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data->pad_base = sys_read32(cfg->reg_base + REG_PAD_BASE_ADDR);
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/* Set to route interrupt through IRQ 14 */
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sys_bitfield_clear_bit(data->pad_base[i] + REG_MISCCFG,
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MISCCFG_IRQ_ROUTE_POS);
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}
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/* Set to route interrupt through IRQ 14 */
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sys_bitfield_clear_bit(data->pad_base + REG_MISCCFG,
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MISCCFG_IRQ_ROUTE_POS);
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dev->driver_api = &gpio_intel_apl_api;
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return 0;
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}
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static const struct gpio_intel_apl_config gpio_intel_apl_cfg = {
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.islands = {
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{
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/* North island */
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.reg_base = DT_APL_GPIO_BASE_ADDRESS_0,
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.num_pins = 78,
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},
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{
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/* Northwest island */
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.reg_base = DT_APL_GPIO_BASE_ADDRESS_1,
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.num_pins = 77,
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},
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{
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/* West island */
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.reg_base = DT_APL_GPIO_BASE_ADDRESS_2,
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.num_pins = 47,
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},
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{
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/* Southwest island */
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.reg_base = DT_APL_GPIO_BASE_ADDRESS_3,
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.num_pins = 43,
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},
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},
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};
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#define GPIO_INTEL_APL_DEV_CFG_DATA(dir_l, dir_u, pos, offset, pins) \
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static const struct gpio_intel_apl_config \
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gpio_intel_apl_cfg_##dir_l##_##pos = { \
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.reg_base = DT_APL_GPIO_BASE_ADDRESS_##dir_u, \
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.pin_offset = offset, \
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.num_pins = pins, \
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}; \
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\
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static struct gpio_intel_apl_data gpio_intel_apl_data_##dir_l##_##pos; \
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\
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DEVICE_AND_API_INIT(gpio_intel_apl_##dir_l##_##pos, \
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DT_APL_GPIO_LABEL_##dir_u##_##pos, \
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gpio_intel_apl_init, \
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&gpio_intel_apl_data_##dir_l##_##pos, \
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&gpio_intel_apl_cfg_##dir_l##_##pos, \
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&gpio_intel_apl_api)
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static struct gpio_intel_apl_data gpio_intel_apl_data;
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GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 0, 0, 32);
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GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 1, 32, 32);
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GPIO_INTEL_APL_DEV_CFG_DATA(n, N, 2, 32, 14);
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DEVICE_AND_API_INIT(gpio_intel_apl, DT_APL_GPIO_LABEL,
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gpio_intel_apl_init,
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&gpio_intel_apl_data, &gpio_intel_apl_cfg,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_intel_apl_api);
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GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 0, 0, 32);
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GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 1, 32, 32);
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GPIO_INTEL_APL_DEV_CFG_DATA(nw, NW, 2, 32, 13);
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GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 0, 0, 32);
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GPIO_INTEL_APL_DEV_CFG_DATA(w, W, 1, 32, 15);
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GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 0, 0, 32);
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GPIO_INTEL_APL_DEV_CFG_DATA(sw, SW, 1, 32, 11);
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static void gpio_intel_apl_irq_config(struct device *dev)
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{
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IRQ_CONNECT(DT_APL_GPIO_IRQ, DT_APL_GPIO_IRQ_PRIORITY,
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gpio_intel_apl_isr, DEVICE_GET(gpio_intel_apl),
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DT_APL_GPIO_IRQ_SENSE);
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struct device *irq_dev;
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irq_enable(DT_APL_GPIO_IRQ);
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irq_dev = device_get_binding(DT_SHARED_IRQ_SHAREDIRQ0_LABEL);
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__ASSERT(irq_dev != NULL,
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"Failed to get shared IRQ device binding");
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shared_irq_isr_register(irq_dev, gpio_intel_apl_isr, dev);
|
||||
shared_irq_enable(irq_dev, dev);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue