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arm: cortex-m: enhance information dump during HardFault escalation

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When inside an escalated HardFault, we would like to get
more information about the reason for this escalation. We
first check if the reason for thise escalation is an SVC,
which occurs within a priority level that does not allow
it to trigger (e.g. fault or another SVC). If this is true
we set the error reason according to the provided argument.

Only when this is not a synchronous SVC that caused the HF,
do we check the other reasons for HF escalation (e.g. a BF
inside a previous BF).

We also add a case for a debug event, to complete going through
the available flags in HFSR.

Finally we ASSERT if we cannot find the reason for the escalation.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit is contained in:
Ioannis Glaropoulos 2021-06-23 11:28:36 +02:00 • committed by Christopher Friedt
commit f795672743
1 changed files with 11 additions and 3 deletions
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14
arch/arm/core/aarch32/cortex_m/fault.c
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@ -686,9 +686,14 @@ static uint32_t hard_fault(z_arch_esf_t *esf, bool *recoverable)
if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk) != 0) {
PR_EXC(" Bus fault on vector table read");
} else if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk) != 0) {
PR_EXC(" Debug event");
} else if ((SCB->HFSR & SCB_HFSR_FORCED_Msk) != 0) {
PR_EXC(" Fault escalation (see below)");
if (SCB_MMFSR != 0) {
if (z_arm_is_synchronous_svc(esf)) {
PR_EXC("ARCH_EXCEPT with reason %x\n", esf->basic.r0);
reason = esf->basic.r0;
} else if (SCB_MMFSR != 0) {
reason = mem_manage_fault(esf, 1, recoverable);
} else if (SCB_BFSR != 0) {
reason = bus_fault(esf, 1, recoverable);
@ -699,10 +704,13 @@ static uint32_t hard_fault(z_arch_esf_t *esf, bool *recoverable)
secure_fault(esf);
#endif /* CONFIG_ARM_SECURE_FIRMWARE */
} else {
;
__ASSERT(0,
"Fault escalation without FSR info");
}
} else {
;
__ASSERT(0,
"HardFault without HFSR info"
" Shall never occur");
}
#else
#error Unknown ARM architecture