boards: arm: Add support for STM32 Minimum Development Board

Add configuration, documentation, pinmux, fixup and dts support for
STM32F103x8 based Minimum System Development board.

Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com>

arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xx

@@ -1,4 +1,4 @@
-# Kconfig - ST Microelectronics STM32F103RB MCU
+# Kconfig - ST Microelectronics STM32F103XX MCU
 #
 # Copyright (c) 2017, embedjournal.com
 #

boards/arm/stm32_min_dev/Kconfig.board

@@ -0,0 +1,9 @@
+# Kconfig - STM32 Minimum Development Board Configuration
+#
+# Copyright (c) 2017, embedjournal.com
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+config BOARD_STM32_MIN_DEV
+	bool "STM32 Minimum Development Board"
+	depends on SOC_STM32F103X8

boards/arm/stm32_min_dev/Kconfig.defconfig

@@ -0,0 +1,13 @@
+# Kconfig - STM32 Minimum Development Board Configuration
+#
+# Copyright (c) 2017, embedjournal.com
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_STM32_MIN_DEV
+
+config BOARD
+	default stm32_min_dev
+
+endif # BOARD_STM32_MIN_DEV

boards/arm/stm32_min_dev/Makefile

@@ -0,0 +1,2 @@
+# No C files (yet)
+obj- += dummy.o

boards/arm/stm32_min_dev/Makefile.board

@@ -0,0 +1,7 @@
+FLASH_SCRIPT = openocd.sh
+DEBUG_SCRIPT = openocd.sh
+
+OPENOCD_LOAD_CMD = "flash write_image erase ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
+OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
+
+export FLASH_SCRIPT OPENOCD_LOAD_CMD OPENOCD_VERIFY_CMD

boards/arm/stm32_min_dev/board.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2017, embedjournal.com
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+/* On board LED */
+#define LED0_GPIO_PORT	"GPIOB"
+#define LED0_GPIO_PIN	12
+
+#endif /* __INC_BOARD_H */

boards/arm/stm32_min_dev/doc/stm32_min_dev.rst

@@ -0,0 +1,114 @@
+.. _stm32_min_dev:
+
+STM32 Minimum Development Board
+###############################
+
+Overview
+********
+
+The STM32 Minimum Development Board, is a popular and inexpensive
+breadboard-friendly breakout board for the `STM32F103x8`_ CPU. Zephyr
+applications use the stm32_min_dev board configuration to run on these boards.
+
+.. figure:: img/stm32_min_dev.jpg
+     :width: 500px
+     :align: center
+     :height: 350px
+     :alt: STM32 Minimum Development Board
+
+     STM32 Minimum Development Board
+
+As the name suggests, these boards have the bare minimum components required to
+power on the CPU. For practical use, you'll need to add additional components
+and circuits using a breadboard, for example.
+
+Pin Mapping
+===========
+
+This port is a starting point for your own customizations and not a complete
+port for a specific board. Most of the GPIOs on the STM32 SoC has been exposed
+in the external header with silk screen labels that match the SoC's pin names.
+
+Each board vendor has their own variations in pin mapping on their boards'
+external connectors and placement of components. Many vendors use port PB12 for
+connecting an LED, so only this device is supported by our Zephyr port.
+Additional device support is left for the user to implement.
+
+More information on hooking up peripherals and lengthy how to articles can be
+found at `EmbedJoural`_.
+
+STLinkV2 connection:
+====================
+
+The board can be flashed by using STLinkV2 with the following connections.
+
++------------------------+
+| Pin    | STLINKv2      |
++========+===============|
+| G      | GND           |
+| CLK    | Clock         |
+| IO     | SW IO         |
+| V3     | VCC           |
++--------+---------------+
+
+Boot Configuration
+==================
+
+The boot configuration for this board is configured through jumpers on B0 (Boot 0)
+and B1 (Boot 1). The pins B0 and B1 are present in between logic 0 and 1 lines. The
+silk screen on the PCB reads BX- or BX+ to indicate 0 and 1 logic lines for B0 and B1
+respectively.
+
++-----------------------------------------------------------------------------------+
+| Boot 1 | Boot 0 | Boot Mode         | Aliasing                                    |
++========+========+===================+=============================================+
+| X      | 0      | Main Flash Memory | Main flash memory is selected as boot space |
+| 0      | 1      | System Memory     | System memory is selected as boot space     |
+| 1      | 1      | Embedded SRAM     | Embedded SRAM is selected as boot space     |
++--------+--------+-------------------+---------------------------------------------+
+
+
+Supported Features
+==================
+
+The on board 8Mhz crystal is used to produce a 72Mhz system clock with PLL.
+The stm32_min_dev board configuration supports the following hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component     |
++===========+============+======================+
+| NVIC      | on-chip    | nested vectored      |
+|           |            | interrupt controller |
++-----------+------------+----------------------+
+| SYSTICK   | on-chip    | system clock         |
++-----------+------------+----------------------+
+| UART      | on-chip    | serial port          |
++-----------+------------+----------------------+
+| GPIO      | on-chip    | gpio                 |
++-----------+------------+----------------------+
+
+Other hardware features are not supported by the Zephyr kernel.
+
+Building and Flashing Zephyr onto stm32_min_dev
+***********************************************
+
+You can build any of the Zephyr samples with,
+
+  .. code-block:: console
+
+      $ cd $<zephyr_root_path>
+      $ source zephyr-env.sh
+      $ make -C samples/basic/blinky BOARD=stm32_min_dev
+
+Flashing the Zephyr kernel onto stm32_min_dev requires the popular ST-Link
+debugger/programmer. This port comes with support for doing just that with the
+flash target.
+
+  .. code-block:: console
+
+      $ make -C samples/basic/blinky BOARD=stm32_min_dev flash
+
+.. _STM32F103x8:
+        http://www.st.com/resource/en/datasheet/stm32f103c8.pdf
+.. _EmbedJournal:
+        https://embedjournal.com/tag/stm32-min-dev/

boards/arm/stm32_min_dev/stm32_min_dev.yaml

@@ -0,0 +1,8 @@
+identifier: stm32_min_dev
+name: STM32-MIN-DEV
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gccarmemb
+ram: 20

boards/arm/stm32_min_dev/stm32_min_dev_defconfig

@@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_BOARD_STM32_MIN_DEV=y
+CONFIG_SOC_FAMILY_STM32=y
+CONFIG_SOC_SERIES_STM32F1X=y
+CONFIG_SOC_STM32F103X8=y
+CONFIG_CORTEX_M_SYSTICK=y
+
+# 72MHz system clock
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
+
+# enable uart driver
+CONFIG_SERIAL=y
+CONFIG_UART_STM32=y
+
+# enable USART1
+CONFIG_UART_STM32_PORT_1=y
+
+# enable console on this port by default
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_1"
+
+# enable pinmux
+CONFIG_PINMUX=y
+CONFIG_PINMUX_STM32=y
+
+# enable GPIO ports A, B
+CONFIG_GPIO=y
+CONFIG_GPIO_STM32=y
+CONFIG_GPIO_STM32_PORTA=y
+CONFIG_GPIO_STM32_PORTB=y
+CONFIG_GPIO_STM32_PORTC=n
+CONFIG_GPIO_STM32_PORTD=n
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
+CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
+
+# use HSE as PLL input
+CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
+# produce 72MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_XTPRE=n
+CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
+CONFIG_CLOCK_STM32_AHB_PRESCALER=1
+
+# APB1 clock must not exceed 36MHz limit
+CONFIG_CLOCK_STM32_APB1_PRESCALER=2
+CONFIG_CLOCK_STM32_APB2_PRESCALER=0

boards/arm/stm32_min_dev/support/openocd.cfg

@@ -0,0 +1,17 @@
+source [find interface/stlink-v2.cfg]
+
+# Work-area size (RAM size) = 20kB
+set WORKAREASIZE 0x5000
+
+source [find target/stm32f1x.cfg]
+
+$_TARGETNAME configure -event gdb-attach {
+        echo "Debugger attaching: halting execution"
+        reset halt
+        gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+        echo "Debugger detaching: resuming execution"
+        resume
+}

drivers/pinmux/Makefile

@@ -23,6 +23,7 @@ obj-$(CONFIG_BOARD_DISCO_L475_IOT1) += stm32/pinmux_board_disco_l475_iot1.o
 obj-$(CONFIG_BOARD_STM32L496G_DISCO) += stm32/pinmux_board_stm32l496g_disco.o
 obj-$(CONFIG_BOARD_OLIMEXINO_STM32) += stm32/pinmux_board_olimexino_stm32.o
 obj-$(CONFIG_BOARD_STM32_MINI_A15) += stm32/pinmux_board_stm32_mini_a15.o
+obj-$(CONFIG_BOARD_STM32_MIN_DEV) += stm32/pinmux_board_stm32_min_dev.o
 obj-$(CONFIG_PINMUX_QMSI) += pinmux_qmsi.o
 obj-$(CONFIG_PINMUX_FE310) += pinmux_fe310.o
 obj-$(CONFIG_PINMUX_CC2650) += pinmux_cc2650.o

drivers/pinmux/stm32/pinmux_board_stm32_min_dev.c

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2017, embedjournal.com
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <pinmux.h>
+#include <sys_io.h>
+#include "pinmux/pinmux.h"
+
+#include "pinmux_stm32.h"
+
+/* pin assignments for STM32_MIN_DEV board */
+static const struct pin_config pinconf[] = {
+#ifdef CONFIG_UART_STM32_PORT_1
+	{STM32_PIN_PA9,  STM32F1_PINMUX_FUNC_PA9_USART1_TX},
+	{STM32_PIN_PA10, STM32F1_PINMUX_FUNC_PA10_USART1_RX},
+#endif	/* CONFIG_UART_STM32_PORT_1 */
+#ifdef CONFIG_UART_STM32_PORT_2
+	{STM32_PIN_PA2, STM32F1_PINMUX_FUNC_PA2_USART2_TX},
+	{STM32_PIN_PA3, STM32F1_PINMUX_FUNC_PA3_USART2_RX},
+#endif	/* CONFIG_UART_STM32_PORT_2 */
+#ifdef CONFIG_UART_STM32_PORT_3
+	{STM32_PIN_PB10, STM32F1_PINMUX_FUNC_PB10_USART3_TX},
+	{STM32_PIN_PB11, STM32F1_PINMUX_FUNC_PB11_USART3_RX},
+#endif	/* CONFIG_UART_STM32_PORT_3 */
+};
+
+static int pinmux_stm32_init(struct device *port)
+{
+	ARG_UNUSED(port);
+
+	stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf));
+
+	return 0;
+}
+
+SYS_INIT(pinmux_stm32_init, PRE_KERNEL_1, CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY);

dts/arm/Makefile

@@ -42,5 +42,7 @@ dtb-$(CONFIG_BOARD_ARDUINO_DUE)		=	arduino_due.dts_compiled
 dtb-$(CONFIG_BOARD_SAM4S_XPLAINED)	=	sam4s_xplained.dts_compiled
 dtb-$(CONFIG_BOARD_OLIMEX_STM32_E407)	=	olimex_stm32_e407.dts_compiled
 dtb-$(CONFIG_BOARD_CC2650_SENSORTAG)	= 	cc2650_sensortag.dts_compiled
+dtb-$(CONFIG_BOARD_STM32_MIN_DEV)	=	stm32_min_dev.dts_compiled
+
 always	:= $(dtb-y)
 endif

dts/arm/stm32_min_dev.dts

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2017, embedjournal.com
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/stm32f103Xb.dtsi>
+
+/ {
+	model = "STM32 Minimum Development Board";
+	compatible = "st,stm32_min_dev", "st,stm32f103rb";
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+};
+
+&usart1 {
+	current-speed = <115200>;
+	status = "ok";
+};

dts/arm/stm32_min_dev.fixup

@@ -0,0 +1,26 @@
+/* This file is a temporary workaround for mapping of the generated information
+ * to the current driver definitions.  This will be removed when the drivers
+ * are modified to handle the generated information, or the mapping of
+ * generated data matches the driver definitions.
+ */
+
+
+#define CONFIG_NUM_IRQ_PRIO_BITS	ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS	ST_STM32_USART_40013800_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_1_BAUD_RATE	ST_STM32_USART_40013800_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_1_IRQ_PRI	ST_STM32_USART_40013800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_PORT_1_NAME		ST_STM32_USART_40013800_LABEL
+#define PORT_1_IRQ				ST_STM32_USART_40013800_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS	ST_STM32_USART_40004400_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_2_BAUD_RATE	ST_STM32_USART_40004400_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_2_IRQ_PRI	ST_STM32_USART_40004400_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_PORT_2_NAME		ST_STM32_USART_40004400_LABEL
+#define PORT_2_IRQ				ST_STM32_USART_40004400_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS	ST_STM32_USART_40004800_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_3_BAUD_RATE	ST_STM32_USART_40004800_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_3_IRQ_PRI	ST_STM32_USART_40004800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_PORT_3_NAME		ST_STM32_USART_40004800_LABEL
+#define PORT_3_IRQ				ST_STM32_USART_40004800_IRQ_0