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espi/it8xxx2: enable EC to accept port 81 cycle

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This allows EC to accept 2 bytes of port 80 data written from the Host.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li 2024-05-03 15:37:39 +08:00 • committed by Anas Nashif
commit f76f2928f1
3 changed files with 29 additions and 3 deletions
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15
drivers/espi/Kconfig.it8xxx2
View file

@ -127,4 +127,19 @@ config ESPI_IT8XXX2_PNPCFG_DEVICE_KBC_MOUSE
With this option enabled, EC will send IRQ12 signal to host when the With this option enabled, EC will send IRQ12 signal to host when the
KBC mouse output buffer is full. KBC mouse output buffer is full.
# On IT8xxx2 series, this configuration option has limitation:
# Port 80 and 81 I/O cycles share the same interrupt source and there is no
# status bit to indicate which cycle triggered the interrupt and data registers
# of these two ports are read only. Hence EC have to read these two data
# registers at the same time in the ISR.
# It means that the Host must alwasy write 2 bytes of data to port 80 otherwise
# port 81 data will not be updated.
config ESPI_IT8XXX2_PORT_81_CYCLE
bool "EC accepts 0x81 I/O cycle from eSPI transaction"
depends on ESPI_PERIPHERAL_DEBUG_PORT_80
help
With this option enabled, EC will accept 0x81 I/O cycle from the Host.
This allows EC to accept 2 bytes of port 80 data written from the Host.
(e.g. using iotools: iotools io_write16 0x80 0x1234)
endif #ESPI_IT8XXX2 endif #ESPI_IT8XXX2

11
drivers/espi/espi_it8xxx2.c
View file

@ -517,7 +517,11 @@ static void port80_it8xxx2_isr(const struct device *dev)
ESPI_PERIPHERAL_NODATA ESPI_PERIPHERAL_NODATA
}; };
if (IS_ENABLED(CONFIG_ESPI_IT8XXX2_PORT_81_CYCLE)) {
evt.evt_data = gctrl->GCTRL_P80HDR | (gctrl->GCTRL_P81HDR << 8);
} else {
evt.evt_data = gctrl->GCTRL_P80HDR; evt.evt_data = gctrl->GCTRL_P80HDR;
}
/* Write 1 to clear this bit */ /* Write 1 to clear this bit */
gctrl->GCTRL_P80H81HSR |= BIT(0); gctrl->GCTRL_P80H81HSR |= BIT(0);
@ -529,8 +533,13 @@ static void port80_it8xxx2_init(const struct device *dev)
ARG_UNUSED(dev); ARG_UNUSED(dev);
struct gctrl_it8xxx2_regs *const gctrl = ESPI_IT8XXX2_GET_GCTRL_BASE; struct gctrl_it8xxx2_regs *const gctrl = ESPI_IT8XXX2_GET_GCTRL_BASE;
/* Accept Port 80h Cycle */ /* Accept Port 80h (and 81h) Cycle */
if (IS_ENABLED(CONFIG_ESPI_IT8XXX2_PORT_81_CYCLE)) {
gctrl->GCTRL_SPCTRL1 |=
(IT8XXX2_GCTRL_ACP80 | IT8XXX2_GCTRL_ACP81);
} else {
gctrl->GCTRL_SPCTRL1 |= IT8XXX2_GCTRL_ACP80; gctrl->GCTRL_SPCTRL1 |= IT8XXX2_GCTRL_ACP80;
}
IRQ_CONNECT(IT8XXX2_PORT_80_IRQ, 0, port80_it8xxx2_isr, IRQ_CONNECT(IT8XXX2_PORT_80_IRQ, 0, port80_it8xxx2_isr,
DEVICE_DT_INST_GET(0), 0); DEVICE_DT_INST_GET(0), 0);
irq_enable(IT8XXX2_PORT_80_IRQ); irq_enable(IT8XXX2_PORT_80_IRQ);

2
soc/ite/ec/common/chip_chipregs.h
View file

@ -1661,6 +1661,8 @@ struct gctrl_it8xxx2_regs {
#define IT8XXX2_GCTRL_ILM0_ENABLE BIT(0) #define IT8XXX2_GCTRL_ILM0_ENABLE BIT(0)
/* Accept Port 80h Cycle */ /* Accept Port 80h Cycle */
#define IT8XXX2_GCTRL_ACP80 BIT(6) #define IT8XXX2_GCTRL_ACP80 BIT(6)
/* Accept Port 81h Cycle */
#define IT8XXX2_GCTRL_ACP81 BIT(3)
/* USB Debug Enable */ /* USB Debug Enable */
#define IT8XXX2_GCTRL_MCCR_USB_EN BIT(7) #define IT8XXX2_GCTRL_MCCR_USB_EN BIT(7)
/* USB Pad Power-On Enable */ /* USB Pad Power-On Enable */