From f7538f0005fbbe70d92d1535656f4fc84e2d42a0 Mon Sep 17 00:00:00 2001 From: Mazen NEIFER Date: Fri, 20 Jan 2017 20:52:29 +0100 Subject: [PATCH] Xtensa port: Added support in arch/cpu.h for Xtensa cores. Change-Id: If4a053f6164fd2fa30f148e6e907f662cda50722 Signed-off-by: Mazen NEIFER --- include/arch/cpu.h | 2 + include/arch/xtensa/arch.h | 106 +++++++++++++++++++++++++++++++++++++ include/arch/xtensa/exc.h | 57 ++++++++++++++++++++ 3 files changed, 165 insertions(+) create mode 100644 include/arch/xtensa/arch.h create mode 100644 include/arch/xtensa/exc.h diff --git a/include/arch/cpu.h b/include/arch/cpu.h index 41f646a1e65..ef79bc1b2cb 100644 --- a/include/arch/cpu.h +++ b/include/arch/cpu.h @@ -19,6 +19,8 @@ #include #elif defined(CONFIG_RISCV32) #include +#elif defined(CONFIG_XTENSA) +#include #else #error "Unknown Architecture" #endif diff --git a/include/arch/xtensa/arch.h b/include/arch/xtensa/arch.h new file mode 100644 index 00000000000..fc9d69f07a8 --- /dev/null +++ b/include/arch/xtensa/arch.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2016 Cadence Design Systems, Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file + * @brief Xtensa specific kernel interface header + * This header contains the Xtensa specific kernel interface. It is included + * by the generic kernel interface header (include/arch/cpu.h) + */ + +#ifndef _ARCH_IFACE_H +#define _ARCH_IFACE_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) +#include +#include +#include + +#define STACK_ALIGN 16 +#define OCTET_TO_SIZEOFUNIT(X) (X) +#define SIZEOFUNIT_TO_OCTET(X) (X) + +#define _NANO_ERR_HW_EXCEPTION (0) /* MPU/Bus/Usage fault */ +#define _NANO_ERR_INVALID_TASK_EXIT (1) /* Invalid task exit */ +#define _NANO_ERR_STACK_CHK_FAIL (2) /* Stack corruption detected */ +#define _NANO_ERR_ALLOCATION_FAIL (3) /* Kernel Allocation Failure */ + +/* Xtensa GPRs are often designated by two different names */ +#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; } + +#include + +#define find_lsb_set __builtin_ffs +#define find_msb_set __builtin_clz + +/* internal routine documented in C file, needed by IRQ_CONNECT() macro */ +extern void _irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags); + + +/** + * Configure a static interrupt. + * + * All arguments must be computable by the compiler at build time; if this + * can't be done use irq_connect_dynamic() instead. + * + * Internally this function does a few things: + * + * 1. The enum statement has no effect but forces the compiler to only + * accept constant values for the irq_p parameter, very important as the + * numerical IRQ line is used to create a named section. + * + * 2. An instance of _isr_table_entry is created containing the ISR and its + * parameter. If you look at how _sw_isr_table is created, each entry in the + * array is in its own section named by the IRQ line number. What we are doing + * here is to override one of the default entries (which points to the + * spurious IRQ handler) with what was supplied here. + * + * 3. The priority level for the interrupt is configured by a call to + * _irq_priority_set() + * + * @param irq_p IRQ line number + * @param priority_p Interrupt priority + * @param isr_p Interrupt service routine + * @param isr_param_p ISR parameter + * @param flags_p IRQ options + * + * @return The vector assigned to this interrupt + */ +#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \ +({ \ + enum { IRQ = irq_p }; \ + static struct _isr_table_entry \ + _CONCAT(_isr_irq, irq_p) \ + __attribute__ ((used)) \ + __attribute__ ((section(\ + STRINGIFY(_CONCAT(.gnu.linkonce.d.isr_irq, irq_p)))\ + )) = {isr_param_p, isr_p}; \ + _irq_priority_set(irq_p, priority_p, flags_p); \ + irq_p; \ +}) +#endif /* !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) */ +#ifdef __cplusplus +} +#endif + +#endif /* _ARCH_IFACE_H */ diff --git a/include/arch/xtensa/exc.h b/include/arch/xtensa/exc.h new file mode 100644 index 00000000000..ba2e24abea4 --- /dev/null +++ b/include/arch/xtensa/exc.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * Copyright (c) 2016 Cadence Design Systems, Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file + * @brief Xtensa public exception handling + * + * Xtensa-specific nanokernel exception handling interface. Included by + * arch/xtensa/arch.h. + */ + +#ifndef _ARCH_XTENSA_EXC_H_ +#define _ARCH_XTENSA_EXC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef _ASMLANGUAGE +#else +/** + * @brief Nanokernel Exception Stack Frame + * + * A pointer to an "exception stack frame" (ESF) is passed as an argument + * to exception handlers registered via nanoCpuExcConnect(). + */ +struct __esf { + /* XXX - not finished yet */ + sys_define_gpr_with_alias(a1, sp); + uint32_t pc; +}; + +typedef struct __esf NANO_ESF; +extern const NANO_ESF _default_esf; +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARCH_XTENSA_EXC_H_ */