diff --git a/boards/arm/mec2016evb_assy6797/CMakeLists.txt b/boards/arm/mec2016evb_assy6797/CMakeLists.txt
deleted file mode 100644
index 17fd9d4425c..00000000000
--- a/boards/arm/mec2016evb_assy6797/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (c) 2019 Intel Corporation
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-zephyr_library()
-zephyr_library_sources(pinmux.c)
diff --git a/boards/arm/mec2016evb_assy6797/Kconfig.board b/boards/arm/mec2016evb_assy6797/Kconfig.board
deleted file mode 100644
index 0ab279fccde..00000000000
--- a/boards/arm/mec2016evb_assy6797/Kconfig.board
+++ /dev/null
@@ -1,6 +0,0 @@
-# Copyright (c) 2019, Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_MEC2016EVB_ASSY6797
-	bool "Microchip MEC2016 EVB ASSY 6797 Development board"
-	depends on SOC_MEC1701_QSZ
diff --git a/boards/arm/mec2016evb_assy6797/Kconfig.defconfig b/boards/arm/mec2016evb_assy6797/Kconfig.defconfig
deleted file mode 100644
index fd416a22c43..00000000000
--- a/boards/arm/mec2016evb_assy6797/Kconfig.defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright (c) 2019 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_MEC2016EVB_ASSY6797
-
-config BOARD
-	default "mec2016evb_assy6797"
-
-endif # BOARD_MEC2016EVB_ASSY6797
diff --git a/boards/arm/mec2016evb_assy6797/doc/index.rst b/boards/arm/mec2016evb_assy6797/doc/index.rst
deleted file mode 100644
index dc03e7fb9a0..00000000000
--- a/boards/arm/mec2016evb_assy6797/doc/index.rst
+++ /dev/null
@@ -1,212 +0,0 @@
-.. _mec2016evb_assy6797:
-
-Microchip MEC2016EVB ASSY6797
-#############################
-
-Overview
-********
-
-The MEC2016EVB_ASSY6797 kit is a development platform to evaluate the
-Microchip MEC1701X series microcontrollers. This board needs to be mated with
-part number MEC170X 144WFBA SOLDER DC ASSY 6801(cpu board) in order to operate.
-
-.. image:: mec2016evb_assy6797.jpg
-     :align: center
-     :alt: MEC2016 EVB ASSY 6797
-
-Hardware
-********
-
-- MEC1701QC2SZ ARM Cortex-M4F Processor
-- 480 KB RAM and 64 KB boot ROM
-- 2 Microchip BC-Link Interconnection bus
-- Keyboard interface
-- ADC & GPIO headers
-- UART0 and UART1
-- FAN0, FAN1, FAN2 headers
-- FAN PWM interface
-- Jtag and Trace ports
-- PECI interface 3.0
-- I2C voltage translator
-- 10 SMBUS headers
-- 3 UDP I2C headers
-- VCI interface
-- 5 independent Hardware Driven PS/2 Ports
-- eSPI header
-- LPC sideband headers
-- 4 Breathing/Blinking LEDs
-- 2 Sockets for SPI NOR chips
-- One reset and VCC_PWRDGD pushbuttons
-
-For more information about the SOC please visit:
-
-- `MEC170x Reference Manual`_
-
-Supported Features
-==================
-
-The mec2016evb_assy6797 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr (at the moment)
-
-The default configuration can be found in the Kconfig file:
-``boards/arm/mec2016evb_assy6797/mec2016evb_assy6797_defconfig``
-
-
-Connections and IOs
-===================
-
-Microchip to provide the schematic for this board.
-
-System Clock
-============
-
-The MEC1701 MCU is configured to use the 48Mhz internal oscillator with the
-on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock
-control register (chapter 4 in user manual)
-
-Serial Port
-===========
-
-UART0 is configured for serial logs.
-
-Jumper settings
-***************
-
-Please follow the jumper settings below to properly demo this
-board. Advanced users may deviate from this recommendation.
-
-Jump setting for MEC2016 EVB Assy 6797 Rev A1p0
-===============================================
-
-Power-related jumpers.
-
-+-------+------+------+------+------+------+-------+-------+
-| JP31  | JP32 | JP35 | JP36 | JP49 | JP50 | JP54  | JP55  |
-+=======+======+======+======+======+======+=======+=======+
-| 1-2   | 1-2  | 1-2  | 1-2  | 1-2  | 1-2  | 1-2   | 1-2   |
-+-------+------+------+------+------+------+-------+-------+
-
-+-------+-------+------+------+------+-------+
-| JP56  | JP57  | JP58 | JP60 | JP61 | JP102 |
-+=======+=======+======+======+======+=======+
-| 1-2   | 1-2   | 1-2  | 1-2  | 1-2  | 2-3   |
-+-------+-------+------+------+------+-------+
-
-These jumpers configure VCC Power good, nRESETI and JTAG_STRAP respectively.
-
-+------------------+-----------+--------------+
-| JP1              | JP2       | JP51         |
-| (VCC Power good) | (nRESETI) | (JTAG_STRAP) |
-+==================+===========+==============+
-| 1-2              | 1-2       | 2-3          |
-+------------------+-----------+--------------+
-
-Each column of the following table illustrates how to enable UART0, JTAG,
-PVT SPI, SHD SPI and LED0-3 respectively.
-
-+---------+--------+-----------+----------+---------+
-| JP27    | JP10   | JP34      | JP75     | JP68    |
-| (UART0) | (JTAG) | (PVT SPI) | (SHD SPI)| (LED0-3)|
-+=========+========+===========+==========+=========+
-| 11-12   | 2-3    | 2-3       | 2-3      | 1-2     |
-+---------+--------+-----------+----------+---------+
-| 8-9     | 5-6    | 5-6       | 5-6      | 3-4     |
-+---------+--------+-----------+----------+---------+
-|         | 8-9    | 8-9       | 8-9      | 5-6     |
-+---------+--------+-----------+----------+---------+
-|         | 11-12  | 11-12     | 11-12    | 7-8     |
-+---------+--------+-----------+----------+---------+
-|         |        | 14-15     | 14-15    |         |
-+---------+--------+-----------+----------+---------+
-|         |        | 17-18     | 17-18    |         |
-+---------+--------+-----------+----------+---------+
-
-Jump settings for MEC170x 144WFBGA Socket DC Assy 6801 Rev B1p0
-===============================================================
-
-The jumper configuration explained above covers the base board. Now the CPU
-board requires the following settings.
-
-+-------+-------+
-| JP1   | JP2   |
-+=======+=======+
-| 1-2   | 2-3   |
-+-------+-------+
-
-Programming and Debugging
-*************************
-
-This board comes with a Cortex ETM port which facilitates tracing and debugging
-using a single physical connection.  In addition, it comes with sockets for
-JTAG only sessions.
-
-Flashing
-========
-
-#. Connect the SPI Dongle ASSY 6791 to J36 (SPI dongle) in order to flash and
-   boot from SHD SPI NOR. Then proceed to flash using Dediprog SF100 or a
-   similar tool for flashing SPI chips. Remember that SPI MISO/MOSI are
-   swapped on dediprog headers!
-
-#. Run your favorite terminal program to listen for output. Under Linux the
-   terminal should be :code:`/dev/ttyACM0`. For example:
-
-   .. code-block:: console
-
-      $ minicom -D /dev/ttyACM0 -o
-
-   The -o option tells minicom not to send the modem initialization
-   string. Connection should be configured as follows:
-
-   - Speed: 115200
-   - Data: 8 bits
-   - Parity: None
-   - Stop bits: 1
-
-#. Connect the MEC2016EVB_ASSY_6797 board to your host computer using the
-   UART0 port. Then build :ref:`hello_world` application. It is important
-   to generate a binary with a new load address, for example do the following::
-
-        ${OBJCOPY} --change-addresses -0xb0000 -O binary -S ${in_elf} ${out_bin}
-
-   Once you obtain the binary, proceed to use the microchip tool mec2016_spi_gen
-   in order to create the final binary. This binary is what you need to flash
-   in your spi nor.
-
-   .. zephyr-app-commands::
-      :zephyr-app: samples/hello_world
-      :board: mec2016evb_assy6797
-      :goals: build flash
-
-   You should see "Hello World! mec2016evb_assy6797" in your terminal.
-
-Debugging
-=========
-
-You can debug an application in the usual way.  Here is an example for the
-:ref:`hello_world` application.
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/hello_world
-   :board: mec2016evb_assy6797
-   :maybe-skip-config:
-   :goals: debug
-
-References
-**********
-.. target-notes::
-
-.. _MEC170x Reference Manual:
-    http://ww1.microchip.com/downloads/en/DeviceDoc/MEC170x-Data-Sheet-DS00002206D.pdf
diff --git a/boards/arm/mec2016evb_assy6797/doc/mec2016evb_assy6797.jpg b/boards/arm/mec2016evb_assy6797/doc/mec2016evb_assy6797.jpg
deleted file mode 100644
index 85e29fc34bb..00000000000
Binary files a/boards/arm/mec2016evb_assy6797/doc/mec2016evb_assy6797.jpg and /dev/null differ
diff --git a/boards/arm/mec2016evb_assy6797/mec2016evb_assy6797.dts b/boards/arm/mec2016evb_assy6797/mec2016evb_assy6797.dts
deleted file mode 100644
index 43b97ac5458..00000000000
--- a/boards/arm/mec2016evb_assy6797/mec2016evb_assy6797.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2018, Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-
-#include <microchip/mec1701qsz.dtsi>
-
-/ {
-	model = "Microchip MEC2016EVB_ASSY6797 evaluation board";
-	compatible = "microchip,mec2016evb_assy679", "microchip,mec1701qsz";
-
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,console = &uart0;
-		zephyr,flash = &flash0;
-	};
-};
-
-&uart0 {
-	status = "okay";
-	current-speed = <115200>;
-};
diff --git a/boards/arm/mec2016evb_assy6797/mec2016evb_assy6797.yaml b/boards/arm/mec2016evb_assy6797/mec2016evb_assy6797.yaml
deleted file mode 100644
index 127dc494ff2..00000000000
--- a/boards/arm/mec2016evb_assy6797/mec2016evb_assy6797.yaml
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright (c) 2019, Intel Corporation
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-identifier: mec2016evb_assy6797
-name: MEC2016 EVB ASSY 6797
-type: mcu
-arch: arm
-toolchain:
-  - zephyr
-  - gnuarmemb
-ram: 64
-flash: 416
diff --git a/boards/arm/mec2016evb_assy6797/mec2016evb_assy6797_defconfig b/boards/arm/mec2016evb_assy6797/mec2016evb_assy6797_defconfig
deleted file mode 100644
index 77a9d525b5e..00000000000
--- a/boards/arm/mec2016evb_assy6797/mec2016evb_assy6797_defconfig
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Copyright (c) 2019, Intel Corporation
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-CONFIG_SOC_MEC1701_QSZ=y
-CONFIG_SOC_SERIES_MEC1701X=y
-CONFIG_BOARD_MEC2016EVB_ASSY6797=y
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
-
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_SERIAL=y
diff --git a/boards/arm/mec2016evb_assy6797/pinmux.c b/boards/arm/mec2016evb_assy6797/pinmux.c
deleted file mode 100644
index d4b1be5c9f5..00000000000
--- a/boards/arm/mec2016evb_assy6797/pinmux.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2018 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <zephyr/kernel.h>
-
-#include "soc.h"
-
-static int board_pinmux_init(void)
-{
-
-	/* See table 2-4 from the Data sheet*/
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay)
-	/* Set muxing, for UART 0 and power up */
-	PCR_INST->CLK_REQ_2_b.UART_0_CLK_REQ = 1;
-	UART0_INST->CONFIG = 0;
-	UART0_INST->ACTIVATE = 1;
-	GPIO_100_137_INST->GPIO_104_PIN_CONTROL_b.MUX_CONTROL = 1;
-	GPIO_100_137_INST->GPIO_105_PIN_CONTROL_b.MUX_CONTROL = 1;
-#endif
-
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
-	/* Set muxing, for UART 1 and power up */
-	PCR_INST->CLK_REQ_2_b.UART_1_CLK_REQ = 1;
-	UART1_INST->CONFIG = 0;
-	UART1_INST->ACTIVATE = 1;
-	GPIO_140_176_INST->GPIO_170_PIN_CONTROL_b.MUX_CONTROL = 2;
-	GPIO_140_176_INST->GPIO_171_PIN_CONTROL_b.MUX_CONTROL = 2;
-	GPIO_100_137_INST->GPIO_113_PIN_CONTROL_b.GPIO_DIRECTION = 1;
-#endif
-	return 0;
-}
-
-SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/dts/arm/microchip/mec1701qsz.dtsi b/dts/arm/microchip/mec1701qsz.dtsi
deleted file mode 100644
index 49923eaec8f..00000000000
--- a/dts/arm/microchip/mec1701qsz.dtsi
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2019 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <arm/armv7-m.dtsi>
-
-/ {
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-m4f";
-			reg = <0>;
-		};
-	};
-
-	flash0: flash@b0000 {
-		reg = <0x000B0000 0x68000>;
-	};
-
-	sram0: memory@118000 {
-		compatible = "mmio-sram";
-		reg = <0x00118000 0x10000>;
-	};
-
-	soc {
-		uart0: uart@400f2400 {
-			compatible = "ns16550";
-			reg = <0x400f2400 0x400>;
-			interrupts = <40 0>;
-			clock-frequency = <1843200>;
-			current-speed = <38400>;
-			reg-shift = <0>;
-			status = "disabled";
-		};
-		uart1: uart@400f2800 {
-			compatible = "ns16550";
-			reg = <0x400f2800 0x400>;
-			interrupts = <41 0>;
-			clock-frequency = <1843200>;
-			current-speed = <38400>;
-			reg-shift = <0>;
-			status = "disabled";
-		};
-	};
-};
-
-&nvic {
-	arm,num-irq-priority-bits = <3>;
-};
diff --git a/soc/arm/microchip_mec/Kconfig.soc b/soc/arm/microchip_mec/Kconfig.soc
index 295434b66d5..85734699608 100644
--- a/soc/arm/microchip_mec/Kconfig.soc
+++ b/soc/arm/microchip_mec/Kconfig.soc
@@ -1,4 +1,4 @@
-# Microchip MEC1701 MCU line
+# Microchip MEC172x, MEC1501 MCU line
 
 # Copyright (c) 2018 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
diff --git a/soc/arm/microchip_mec/common/soc_i2c.c b/soc/arm/microchip_mec/common/soc_i2c.c
index b2e5afbf178..0e33437af98 100644
--- a/soc/arm/microchip_mec/common/soc_i2c.c
+++ b/soc/arm/microchip_mec/common/soc_i2c.c
@@ -53,23 +53,6 @@ static const struct mec_i2c_port mec_i2c_ports[] = {
 	{ 0065, 2, 0066, 2 }, /* VTR3 */
 	{ 0071, 2, 0070, 2 }, /* VTR3 */
 	{ 0150, 1, 0147, 1 }
-#elif defined(CONFIG_SOC_SERIES_MEC1701X)
-	{ 0004, 1, 0003, 1 },
-	{ 0006, 1, 0005, 1 },
-	{ 0155, 1, 0154, 1 },
-	{ 0010, 1, 0007, 1 },
-	{ 0144, 1, 0143, 1 },
-	{ 0142, 1, 0141, 1 },
-	{ 0140, 1, 0132, 1 }, /* VTR2 */
-	{ 0013, 1, 0012, 1 }, /* VTR2 */
-	{ 0150, 1, 0147, 1 },
-	{ 0146, 1, 0145, 1 },
-	{ 0131, 1, 0130, 1 }, /* VTR2 */
-	{ 0xFF, 0, 0xFF, 0 }, /* No I2C Ports 11 - 15 */
-	{ 0xFF, 0, 0xFF, 0 },
-	{ 0xFF, 0, 0xFF, 0 },
-	{ 0xFF, 0, 0xFF, 0 },
-	{ 0xFF, 0, 0xFF, 0 }
 #endif
 };
 
diff --git a/soc/arm/microchip_mec/common/soc_i2c.h b/soc/arm/microchip_mec/common/soc_i2c.h
index 2398b1421bb..e4092b6aebf 100644
--- a/soc/arm/microchip_mec/common/soc_i2c.h
+++ b/soc/arm/microchip_mec/common/soc_i2c.h
@@ -16,8 +16,6 @@
 #define MEC_I2C_PORT_MASK	0xFEFFU
 #elif defined(CONFIG_SOC_MEC1501_HSZ)
 #define MEC_I2C_PORT_MASK	0xFEFFU
-#elif defined(CONFIG_SOC_MEC1701_QSZ)
-#define MEC_I2C_PORT_MASK	0x07FFU
 #endif
 
 #define MCHP_I2C_PORT_0		0
diff --git a/soc/arm/microchip_mec/mec1701/CMakeLists.txt b/soc/arm/microchip_mec/mec1701/CMakeLists.txt
deleted file mode 100644
index 332416ba43b..00000000000
--- a/soc/arm/microchip_mec/mec1701/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_sources(
-  soc.c
-  )
diff --git a/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.mec1701qsz b/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.mec1701qsz
deleted file mode 100644
index 437ec1e44fa..00000000000
--- a/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.mec1701qsz
+++ /dev/null
@@ -1,14 +0,0 @@
-# Microchip MEC1701QSZ MCU
-
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_MEC1701_QSZ
-
-config SOC
-	default "mec1701qsz"
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 48000000
-
-endif # SOC_MEC1701_QSZ
diff --git a/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.series b/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.series
deleted file mode 100644
index 46bbdda6949..00000000000
--- a/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.series
+++ /dev/null
@@ -1,18 +0,0 @@
-# Microchip MEC MCU series configuration options
-
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_MEC1701X
-
-config SOC_SERIES
-	default "mec1701"
-
-config NUM_IRQS
-	# must be >= the highest interrupt number used
-	# - include the UART interrupts
-	#for the moment 42 needs to be corrected in terms of devices added
-	default 42
-
-source "soc/arm/microchip_mec/mec1701/Kconfig.defconfig.mec1701*"
-endif # SOC_SERIES_MEC1701X
diff --git a/soc/arm/microchip_mec/mec1701/Kconfig.series b/soc/arm/microchip_mec/mec1701/Kconfig.series
deleted file mode 100644
index 51d49ce2d32..00000000000
--- a/soc/arm/microchip_mec/mec1701/Kconfig.series
+++ /dev/null
@@ -1,14 +0,0 @@
-# Microchip MEC1701 MCU core series
-
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_MEC1701X
-	bool "Microchip MEC1701X Series"
-	select ARM
-	select CPU_CORTEX_M4
-	select CPU_CORTEX_M_HAS_DWT
-	select SOC_FAMILY_MEC
-	select CPU_HAS_FPU
-	help
-	  Enable support for Microchip MEC Cortex-M4 MCU series
diff --git a/soc/arm/microchip_mec/mec1701/Kconfig.soc b/soc/arm/microchip_mec/mec1701/Kconfig.soc
deleted file mode 100644
index 9464f49f44e..00000000000
--- a/soc/arm/microchip_mec/mec1701/Kconfig.soc
+++ /dev/null
@@ -1,14 +0,0 @@
-# Microchip MEC1701 MCU core series
-
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "MEC1701 Selection"
-	depends on SOC_SERIES_MEC1701X
-
-config SOC_MEC1701_QSZ
-	bool "MEC1701_QSZ"
-	select HAS_MEC_HAL
-
-endchoice
diff --git a/soc/arm/microchip_mec/mec1701/linker.ld b/soc/arm/microchip_mec/mec1701/linker.ld
deleted file mode 100644
index 96ec397da78..00000000000
--- a/soc/arm/microchip_mec/mec1701/linker.ld
+++ /dev/null
@@ -1,9 +0,0 @@
-/* linker.ld - Linker command/script file */
-
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>
diff --git a/soc/arm/microchip_mec/mec1701/soc.c b/soc/arm/microchip_mec/mec1701/soc.c
deleted file mode 100644
index 63c6e699054..00000000000
--- a/soc/arm/microchip_mec/mec1701/soc.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2018 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <soc.h>
-#include <zephyr/kernel.h>
-
-
-static int soc_init(void)
-{
-	__IO uint32_t *girc_enable_set;
-
-	__enable_irq();
-
-	/* Enable clocks for Interrupts and CPU */
-	PCR_INST->CLK_REQ_1_b.INT_CLK_REQ = 1;
-	PCR_INST->CLK_REQ_1_b.PROCESSOR_CLK_REQ = 1;
-
-	/* Route all interrupts from EC to NVIC */
-	EC_REG_BANK_INST->INTERRUPT_CONTROL = 0x1;
-	for (girc_enable_set = (uint32_t *)&INTS_INST->GIRQ08_EN_SET;
-	     girc_enable_set <= &INTS_INST->GIRQ15_EN_SET;
-	     girc_enable_set += 5) {
-	/* This probably will require tuning, but drawing 8.2 also
-	illustrates how to disable spurious interrupts */
-		*girc_enable_set = 0xFFFFFFFF;
-	}
-
-	return 0;
-}
-
-SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/arm/microchip_mec/mec1701/soc.h b/soc/arm/microchip_mec/mec1701/soc.h
deleted file mode 100644
index 522b9cd86bf..00000000000
--- a/soc/arm/microchip_mec/mec1701/soc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2018 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __MEC_SOC_H
-#define __MEC_SOC_H
-
-#define SYSCLK_DEFAULT_IOSC_HZ MHZ(48)
-
-#ifndef _ASMLANGUAGE
-
-#include "MCHP_MEC1701.h"
-
-#endif
-
-#endif