soc: nxp: imxrt: Clang format flexspi_nor_config.h
Check compliance is not allowing changes to this file without running clang-format. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
Declan Snyder
Alberto Escolar
parent
9d9d2f8178
commit
f6bfedf114
1 changed files with 86 additions and 87 deletions
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@ -12,105 +12,104 @@
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#include <zephyr/types.h>
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#include "fsl_common.h"
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#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)
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#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)
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#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL)
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#define FLEXSPI_CFG_BLK_SIZE (512)
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#define FLEXSPI_CFG_BLK_SIZE (512)
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#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
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#define CMD_INDEX_READ 0
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#define CMD_INDEX_READSTATUS 1
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#define CMD_INDEX_READ 0
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#define CMD_INDEX_READSTATUS 1
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#define CMD_INDEX_WRITEENABLE 2
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#define CMD_INDEX_WRITE 4
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#define CMD_INDEX_WRITE 4
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#define CMD_LUT_SEQ_IDX_READ 0
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#define CMD_LUT_SEQ_IDX_READSTATUS 1
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#define CMD_LUT_SEQ_IDX_READ 0
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#define CMD_LUT_SEQ_IDX_READSTATUS 1
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#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
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#define CMD_LUT_SEQ_IDX_WRITE 9
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#define CMD_LUT_SEQ_IDX_WRITE 9
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#define CMD_SDR 0x01
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#define CMD_DDR 0x21
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#define RADDR_SDR 0x02
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#define RADDR_DDR 0x22
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#define CADDR_SDR 0x03
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#define CADDR_DDR 0x23
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#define MODE1_SDR 0x04
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#define MODE1_DDR 0x24
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#define MODE2_SDR 0x05
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#define MODE2_DDR 0x25
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#define MODE4_SDR 0x06
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#define MODE4_DDR 0x26
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#define MODE8_SDR 0x07
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#define MODE8_DDR 0x27
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#define WRITE_SDR 0x08
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#define WRITE_DDR 0x28
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#define READ_SDR 0x09
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#define READ_DDR 0x29
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#define LEARN_SDR 0x0A
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#define LEARN_DDR 0x2A
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#define DATSZ_SDR 0x0B
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#define DATSZ_DDR 0x2B
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#define DUMMY_SDR 0x0C
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#define DUMMY_DDR 0x2C
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#define CMD_SDR 0x01
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#define CMD_DDR 0x21
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#define RADDR_SDR 0x02
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#define RADDR_DDR 0x22
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#define CADDR_SDR 0x03
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#define CADDR_DDR 0x23
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#define MODE1_SDR 0x04
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#define MODE1_DDR 0x24
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#define MODE2_SDR 0x05
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#define MODE2_DDR 0x25
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#define MODE4_SDR 0x06
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#define MODE4_DDR 0x26
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#define MODE8_SDR 0x07
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#define MODE8_DDR 0x27
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#define WRITE_SDR 0x08
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#define WRITE_DDR 0x28
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#define READ_SDR 0x09
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#define READ_DDR 0x29
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#define LEARN_SDR 0x0A
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#define LEARN_DDR 0x2A
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#define DATSZ_SDR 0x0B
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#define DATSZ_DDR 0x2B
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#define DUMMY_SDR 0x0C
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#define DUMMY_DDR 0x2C
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#define DUMMY_RWDS_SDR 0x0D
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#define DUMMY_RWDS_DDR 0x2D
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#define JMP_ON_CS 0x1F
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#define STOP 0
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#define JMP_ON_CS 0x1F
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#define STOP 0
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#define FLEXSPI_1PAD 0
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#define FLEXSPI_2PAD 1
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#define FLEXSPI_4PAD 2
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#define FLEXSPI_8PAD 3
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#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
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(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \
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FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
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FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
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(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \
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FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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/* For flexspi_mem_config.serialClkFreq */
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#if defined(CONFIG_SOC_MIMXRT1011)
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enum {
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_120MHz = 7,
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kFlexSpiSerialClk_133MHz = 8,
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};
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#elif defined(CONFIG_SOC_MIMXRT1015) || defined(CONFIG_SOC_MIMXRT1021) || \
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#elif defined(CONFIG_SOC_MIMXRT1015) || defined(CONFIG_SOC_MIMXRT1021) || \
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defined(CONFIG_SOC_MIMXRT1024)
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enum {
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_133MHz = 7,
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};
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#elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052) || \
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#elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052) || \
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defined(CONFIG_SOC_SERIES_IMXRT11XX)
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enum {
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_133MHz = 7,
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kFlexSpiSerialClk_166MHz = 8,
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kFlexSpiSerialClk_200MHz = 9,
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};
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#elif defined(CONFIG_SOC_MIMXRT1061) || defined(CONFIG_SOC_MIMXRT1062) || \
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#elif defined(CONFIG_SOC_MIMXRT1061) || defined(CONFIG_SOC_MIMXRT1062) || \
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defined(CONFIG_SOC_MIMXRT1062) || defined(CONFIG_SOC_MIMXRT1064)
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enum {
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_120MHz = 7,
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kFlexSpiSerialClk_133MHz = 8,
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@ -131,7 +130,7 @@ enum {
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kFlexSPIReadSampleClk_LoopbackInternally = 0,
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kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
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kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
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kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
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kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
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};
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/* For flexspi_mem_config.controllerMiscOption */
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@ -139,15 +138,15 @@ enum {
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/* !< Bit for Differential clock enable */
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kFlexSpiMiscOffset_DiffClkEnable = 0,
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/* !< Bit for CK2 enable */
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kFlexSpiMiscOffset_Ck2Enable = 1,
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kFlexSpiMiscOffset_Ck2Enable = 1,
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/* !< Bit for Parallel mode enable */
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kFlexSpiMiscOffset_ParallelEnable = 2,
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/* !< Bit for Word Addressable enable */
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kFlexSpiMiscOffset_WordAddressableEnable = 3,
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kFlexSpiMiscOffset_WordAddressableEnable = 3,
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/* !< Bit for Safe Configuration Frequency enable */
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kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,
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kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,
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/* !< Bit for Pad setting override enable */
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kFlexSpiMiscOffset_PadSettingOverrideEnable = 5,
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kFlexSpiMiscOffset_PadSettingOverrideEnable = 5,
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/* !< Bit for DDR clock configuration indication. */
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kFlexSpiMiscOffset_DdrModeEnable = 6,
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};
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@ -155,20 +154,20 @@ enum {
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/* For flexspi_mem_config.deviceType */
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enum {
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/* !< Flash devices are Serial NOR */
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kFlexSpiDeviceType_SerialNOR = 1,
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kFlexSpiDeviceType_SerialNOR = 1,
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/* !< Flash devices are Serial NAND */
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kFlexSpiDeviceType_SerialNAND = 2,
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kFlexSpiDeviceType_SerialNAND = 2,
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/* !< Flash devices are Serial RAM/HyperFLASH */
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kFlexSpiDeviceType_SerialRAM = 3,
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kFlexSpiDeviceType_SerialRAM = 3,
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/* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */
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kFlexSpiDeviceType_MCP_NOR_NAND = 0x12,
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/* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */
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kFlexSpiDeviceType_MCP_NOR_RAM = 0x13,
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kFlexSpiDeviceType_MCP_NOR_RAM = 0x13,
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};
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/* For flexspi_mem_config.sflashPadType */
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enum {
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kSerialFlash_1Pad = 1,
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kSerialFlash_1Pad = 1,
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kSerialFlash_2Pads = 2,
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kSerialFlash_4Pads = 4,
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kSerialFlash_8Pads = 8,
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@ -290,27 +289,27 @@ struct flexspi_mem_config_t {
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uint32_t reserved4[4];
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};
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#define NOR_CMD_INDEX_READ CMD_INDEX_READ
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#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS
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#define NOR_CMD_INDEX_READ CMD_INDEX_READ
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#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS
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#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE
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#define NOR_CMD_INDEX_ERASESECTOR 3
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#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE
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#define NOR_CMD_INDEX_CHIPERASE 5
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#define NOR_CMD_INDEX_DUMMY 6
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#define NOR_CMD_INDEX_ERASEBLOCK 7
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#define NOR_CMD_INDEX_CHIPERASE 5
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#define NOR_CMD_INDEX_DUMMY 6
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#define NOR_CMD_INDEX_ERASEBLOCK 7
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#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS
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#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4
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#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
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#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE
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#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
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#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13
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#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14
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#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4
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#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
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#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE
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#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
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#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13
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#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14
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#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15
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struct flexspi_nor_config_t {
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/* !< Common memory configuration info via FlexSPI */
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