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soc: nxp: imxrt: Clang format flexspi_nor_config.h

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Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
Declan Snyder 2024-08-13 11:41:22 -05:00 • committed by Alberto Escolar
commit f6bfedf114
1 changed files with 86 additions and 87 deletions
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173
soc/nxp/imxrt/flexspi_nor_config.h
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@ -12,105 +12,104 @@
#include <zephyr/types.h> #include <zephyr/types.h>
#include "fsl_common.h" #include "fsl_common.h"
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) #define FLEXSPI_CFG_BLK_TAG (0x42464346UL)
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL)
#define FLEXSPI_CFG_BLK_SIZE (512) #define FLEXSPI_CFG_BLK_SIZE (512)
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
#define CMD_INDEX_READ 0 #define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1 #define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2 #define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4 #define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0 #define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1 #define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 #define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9 #define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01 #define CMD_SDR 0x01
#define CMD_DDR 0x21 #define CMD_DDR 0x21
#define RADDR_SDR 0x02 #define RADDR_SDR 0x02
#define RADDR_DDR 0x22 #define RADDR_DDR 0x22
#define CADDR_SDR 0x03 #define CADDR_SDR 0x03
#define CADDR_DDR 0x23 #define CADDR_DDR 0x23
#define MODE1_SDR 0x04 #define MODE1_SDR 0x04
#define MODE1_DDR 0x24 #define MODE1_DDR 0x24
#define MODE2_SDR 0x05 #define MODE2_SDR 0x05
#define MODE2_DDR 0x25 #define MODE2_DDR 0x25
#define MODE4_SDR 0x06 #define MODE4_SDR 0x06
#define MODE4_DDR 0x26 #define MODE4_DDR 0x26
#define MODE8_SDR 0x07 #define MODE8_SDR 0x07
#define MODE8_DDR 0x27 #define MODE8_DDR 0x27
#define WRITE_SDR 0x08 #define WRITE_SDR 0x08
#define WRITE_DDR 0x28 #define WRITE_DDR 0x28
#define READ_SDR 0x09 #define READ_SDR 0x09
#define READ_DDR 0x29 #define READ_DDR 0x29
#define LEARN_SDR 0x0A #define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A #define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B #define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B #define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C #define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C #define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D #define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D #define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F #define JMP_ON_CS 0x1F
#define STOP 0 #define STOP 0
#define FLEXSPI_1PAD 0 #define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1 #define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2 #define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3 #define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \ (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \
FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
/* For flexspi_mem_config.serialClkFreq */ /* For flexspi_mem_config.serialClkFreq */
#if defined(CONFIG_SOC_MIMXRT1011) #if defined(CONFIG_SOC_MIMXRT1011)
enum { enum {
kFlexSpiSerialClk_30MHz = 1, kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2, kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3, kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4, kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5, kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6, kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_120MHz = 7, kFlexSpiSerialClk_120MHz = 7,
kFlexSpiSerialClk_133MHz = 8, kFlexSpiSerialClk_133MHz = 8,
}; };
#elif defined(CONFIG_SOC_MIMXRT1015) || defined(CONFIG_SOC_MIMXRT1021) || \ #elif defined(CONFIG_SOC_MIMXRT1015) || defined(CONFIG_SOC_MIMXRT1021) || \
defined(CONFIG_SOC_MIMXRT1024) defined(CONFIG_SOC_MIMXRT1024)
enum { enum {
kFlexSpiSerialClk_30MHz = 1, kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2, kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3, kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4, kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5, kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6, kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7, kFlexSpiSerialClk_133MHz = 7,
}; };
#elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052) || \ #elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052) || \
defined(CONFIG_SOC_SERIES_IMXRT11XX) defined(CONFIG_SOC_SERIES_IMXRT11XX)
enum { enum {
kFlexSpiSerialClk_30MHz = 1, kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2, kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3, kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4, kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5, kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6, kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7, kFlexSpiSerialClk_133MHz = 7,
kFlexSpiSerialClk_166MHz = 8, kFlexSpiSerialClk_166MHz = 8,
kFlexSpiSerialClk_200MHz = 9, kFlexSpiSerialClk_200MHz = 9,
}; };
#elif defined(CONFIG_SOC_MIMXRT1061) || defined(CONFIG_SOC_MIMXRT1062) || \ #elif defined(CONFIG_SOC_MIMXRT1061) || defined(CONFIG_SOC_MIMXRT1062) || \
defined(CONFIG_SOC_MIMXRT1062) || defined(CONFIG_SOC_MIMXRT1064) defined(CONFIG_SOC_MIMXRT1062) || defined(CONFIG_SOC_MIMXRT1064)
enum { enum {
kFlexSpiSerialClk_30MHz = 1, kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2, kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3, kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4, kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5, kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6, kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_120MHz = 7, kFlexSpiSerialClk_120MHz = 7,
kFlexSpiSerialClk_133MHz = 8, kFlexSpiSerialClk_133MHz = 8,
@ -131,7 +130,7 @@ enum {
kFlexSPIReadSampleClk_LoopbackInternally = 0, kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
}; };
/* For flexspi_mem_config.controllerMiscOption */ /* For flexspi_mem_config.controllerMiscOption */
@ -139,15 +138,15 @@ enum {
/* !< Bit for Differential clock enable */ /* !< Bit for Differential clock enable */
kFlexSpiMiscOffset_DiffClkEnable = 0, kFlexSpiMiscOffset_DiffClkEnable = 0,
/* !< Bit for CK2 enable */ /* !< Bit for CK2 enable */
kFlexSpiMiscOffset_Ck2Enable = 1, kFlexSpiMiscOffset_Ck2Enable = 1,
/* !< Bit for Parallel mode enable */ /* !< Bit for Parallel mode enable */
kFlexSpiMiscOffset_ParallelEnable = 2, kFlexSpiMiscOffset_ParallelEnable = 2,
/* !< Bit for Word Addressable enable */ /* !< Bit for Word Addressable enable */
kFlexSpiMiscOffset_WordAddressableEnable = 3, kFlexSpiMiscOffset_WordAddressableEnable = 3,
/* !< Bit for Safe Configuration Frequency enable */ /* !< Bit for Safe Configuration Frequency enable */
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, kFlexSpiMiscOffset_SafeConfigFreqEnable = 4,
/* !< Bit for Pad setting override enable */ /* !< Bit for Pad setting override enable */
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, kFlexSpiMiscOffset_PadSettingOverrideEnable = 5,
/* !< Bit for DDR clock configuration indication. */ /* !< Bit for DDR clock configuration indication. */
kFlexSpiMiscOffset_DdrModeEnable = 6, kFlexSpiMiscOffset_DdrModeEnable = 6,
}; };
@ -155,20 +154,20 @@ enum {
/* For flexspi_mem_config.deviceType */ /* For flexspi_mem_config.deviceType */
enum { enum {
/* !< Flash devices are Serial NOR */ /* !< Flash devices are Serial NOR */
kFlexSpiDeviceType_SerialNOR = 1, kFlexSpiDeviceType_SerialNOR = 1,
/* !< Flash devices are Serial NAND */ /* !< Flash devices are Serial NAND */
kFlexSpiDeviceType_SerialNAND = 2, kFlexSpiDeviceType_SerialNAND = 2,
/* !< Flash devices are Serial RAM/HyperFLASH */ /* !< Flash devices are Serial RAM/HyperFLASH */
kFlexSpiDeviceType_SerialRAM = 3, kFlexSpiDeviceType_SerialRAM = 3,
/* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */ /* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, kFlexSpiDeviceType_MCP_NOR_NAND = 0x12,
/* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */ /* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, kFlexSpiDeviceType_MCP_NOR_RAM = 0x13,
}; };
/* For flexspi_mem_config.sflashPadType */ /* For flexspi_mem_config.sflashPadType */
enum { enum {
kSerialFlash_1Pad = 1, kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2, kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4, kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8, kSerialFlash_8Pads = 8,
@ -290,27 +289,27 @@ struct flexspi_mem_config_t {
uint32_t reserved4[4]; uint32_t reserved4[4];
}; };
#define NOR_CMD_INDEX_READ CMD_INDEX_READ #define NOR_CMD_INDEX_READ CMD_INDEX_READ
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS #define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE #define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE
#define NOR_CMD_INDEX_ERASESECTOR 3 #define NOR_CMD_INDEX_ERASESECTOR 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE #define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE
#define NOR_CMD_INDEX_CHIPERASE 5 #define NOR_CMD_INDEX_CHIPERASE 5
#define NOR_CMD_INDEX_DUMMY 6 #define NOR_CMD_INDEX_DUMMY 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 #define NOR_CMD_INDEX_ERASEBLOCK 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ #define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS #define NOR_CMD_LUT_SEQ_IDX_READSTATUS CMD_LUT_SEQ_IDX_READSTATUS
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 2
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE CMD_LUT_SEQ_IDX_WRITEENABLE
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI 4
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 #define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 #define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE #define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM CMD_LUT_SEQ_IDX_WRITE
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 #define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 #define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14 #define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD 14
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 #define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15
struct flexspi_nor_config_t { struct flexspi_nor_config_t {
/* !< Common memory configuration info via FlexSPI */ /* !< Common memory configuration info via FlexSPI */