From f61c4ae838f2ff301d53bab05d3763efd39995d6 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Mon, 24 Jan 2022 11:46:58 +0100 Subject: [PATCH] tests/drivers/clock_control: stm32h7_device: Use STM32_DT_CLOCKS_FOO Make use of STM32_DT_CLOCKS_ macros to have the test work conditionally based on alt clock presence. Signed-off-by: Erwan Gouriou --- .../boards/spi1_pllq_2_d1ppre_4.overlay | 11 ++- .../src/test_stm32_clock_configuration.c | 98 ++++++++++++------- 2 files changed, 70 insertions(+), 39 deletions(-) diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pllq_2_d1ppre_4.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pllq_2_d1ppre_4.overlay index e5fd48cb3a3..5cfb5e6da47 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pllq_2_d1ppre_4.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pllq_2_d1ppre_4.overlay @@ -9,6 +9,12 @@ * It is assumed that it is applied after core_init.overlay file. */ +/* With this particular div-q and d1ppre values + * APB2 and PLL_Q clock frequencies are equal. + * This setting is default stm32h7 SPI devices configuration. + * This test config ensures it still works. + */ + &pll { /delete-property/ div-q; div-q = <2>; @@ -21,8 +27,7 @@ &spi1 { /delete-property/ clocks; - clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>, - <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; - clock-names = "reg", "kernel"; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>; + clock-names = "reg"; status = "okay"; }; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c index 403494b077f..85424dcc28d 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c @@ -11,6 +11,16 @@ #include LOG_MODULE_REGISTER(test); +#define DT_DRV_COMPAT st_stm32_spi + +#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT +#define STM32_SPI_OPT_CLOCK_SUPPORT 1 +#else +#define STM32_SPI_OPT_CLOCK_SUPPORT 0 +#endif + +#define DT_NO_CLOCK 0xFFFFU + /* Not device related, but keep it to ensure core clock config is correct */ static void test_sysclk_freq(void) { @@ -25,14 +35,9 @@ static void test_sysclk_freq(void) static void test_spi_clk_config(void) { - struct stm32_pclken spi1_reg_clk_cfg = { - .enr = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), reg, bits), - .bus = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), reg, bus) - }; - struct stm32_pclken spi1_ker_clk_cfg = { - .enr = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), kernel, bits), - .bus = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), kernel, bus) - }; + static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(spi1); + struct stm32_pclken spi1_reg_clk_cfg = pclken[0]; + uint32_t spi1_actual_clk_src, spi1_dt_ker_clk_src; uint32_t spi1_dt_clk_freq, spi1_actual_clk_freq; int r; @@ -45,39 +50,60 @@ static void test_spi_clk_config(void) zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be on"); TC_PRINT("SPI1 reg_clk on\n"); - /* Test clock_on(ker_clk) */ - r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &spi1_ker_clk_cfg); - zassert_true((r == 0), "Could not enable SPI ker_clk"); - TC_PRINT("SPI1 ker_clk on\n"); + if (IS_ENABLED(STM32_SPI_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { + struct stm32_pclken spi1_ker_clk_cfg = pclken[1]; - /* Test ker_clk source */ - spi1_dt_ker_clk_src = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), kernel, bus); - spi1_actual_clk_src = __HAL_RCC_GET_SPI1_SOURCE(); + /* Select ker_clk as device source clock */ + r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &spi1_ker_clk_cfg, + NULL); + zassert_true((r == 0), "Could not enable SPI ker_clk"); + TC_PRINT("SPI1 ker_clk on\n"); - if (spi1_dt_ker_clk_src == STM32_SRC_PLL1_Q) { - zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL, - "Expected SPI src: PLLQ (%d). Actual SPI src: %d", - spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL); - } else if (spi1_dt_ker_clk_src == STM32_SRC_PLL3_P) { - zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3, - "Expected SPI src: PLLQ (%d). Actual SPI src: %d", - spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3); + /* Test ker_clk is configured as device's source clock */ + spi1_dt_ker_clk_src = COND_CODE_1(DT_CLOCKS_HAS_NAME(DT_NODELABEL(spi1), kernel), + (DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), + kernel, bus)), + (DT_NO_CLOCK)); + spi1_actual_clk_src = __HAL_RCC_GET_SPI1_SOURCE(); + + if (spi1_dt_ker_clk_src == STM32_SRC_PLL1_Q) { + zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL, + "Expected SPI src: PLLQ (%d). Actual SPI src: %d", + spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL); + } else if (spi1_dt_ker_clk_src == STM32_SRC_PLL3_P) { + zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3, + "Expected SPI src: PLLQ (%d). Actual SPI src: %d", + spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3); + } else { + zassert_true(1, "Unexpected ker_clk src(%d)", spi1_dt_ker_clk_src); + } + + /* Test get_rate(ker_clk) */ + r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &spi1_ker_clk_cfg, + &spi1_dt_clk_freq); + zassert_true((r == 0), "Could not get SPI clk freq"); + + spi1_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1); + zassert_equal(spi1_dt_clk_freq, spi1_actual_clk_freq, + "Expected SPI clk: (%d). Actual SPI clk: %d", + spi1_dt_clk_freq, spi1_actual_clk_freq); } else { - zassert_true(1, "Unexpected ker_clk src(%d)", spi1_dt_ker_clk_src); + /* No alt clock available, get rate from reg_clk */ + + /* Test get_rate(reg_clk) */ + r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &spi1_reg_clk_cfg, + &spi1_dt_clk_freq); + zassert_true((r == 0), "Could not get SPI clk freq"); + + spi1_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1); + zassert_equal(spi1_dt_clk_freq, spi1_actual_clk_freq, + "Expected SPI clk: (%d). Actual SPI clk: %d", + spi1_dt_clk_freq, spi1_actual_clk_freq); } - /* Test get_rate(ker_clk) */ - r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &spi1_ker_clk_cfg, - &spi1_dt_clk_freq); - zassert_true((r == 0), "Could not get SPI clk freq"); - - spi1_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1); - zassert_equal(spi1_dt_clk_freq, spi1_actual_clk_freq, - "Expected SPI clk: (%d). Actual SPI clk: %d", - spi1_dt_clk_freq, spi1_actual_clk_freq); - /* Test clock_off(reg_clk) */ r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), (clock_control_subsys_t) &spi1_reg_clk_cfg);