arch: arm64: Reserved Cores
Enhanced arch_start_cpu so if a core is not available based on pm_cpu_on return value, booting does not halt. Instead the next core in cpu_node_list will be tried. If the number of CPU nodes described in the device tree is greater than CONFIG_MP_MAX_NUM_CPUS then the extra cores will be reserved and used if any previous cores in the cpu_node_list fail to power on. If the number of cores described in the device tree matches CONFIG_MP_MAX_NUM_CPUS then no cores are in reserve and booting will behave as previous, it will halt. Signed-off-by: Chad Karaginides <quic_chadk@quicinc.com>
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2 changed files with 45 additions and 25 deletions
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@ -159,6 +159,15 @@ config ARM64_SAFE_EXCEPTION_STACK_SIZE
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The stack size of the safe exception stack. The safe exception stack
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requires to be enough to do the stack overflow check.
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config ARM64_FALLBACK_ON_RESERVED_CORES
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bool "To enable fallback on reserved cores"
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help
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Give the ability to define more cores in the device tree than required
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via CONFIG_MP_MAX_NUM_CPUS. The extra cores in the device tree
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become reserved. If there is an issue powering on a core during boot
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then that core will be skipped and the next core in the device tree
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will be used.
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if CPU_CORTEX_A
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config ARMV8_A_NS
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@ -63,7 +63,8 @@ extern void z_arm64_mm_init(bool is_primary_core);
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void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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arch_cpustart_t fn, void *arg)
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{
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int cpu_count, i, j;
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int cpu_count;
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static int i;
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uint64_t cpu_mpid = 0;
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uint64_t master_core_mpid;
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@ -72,41 +73,51 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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master_core_mpid = MPIDR_TO_CORE(GET_MPIDR());
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cpu_count = ARRAY_SIZE(cpu_node_list);
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#ifdef CONFIG_ARM64_FALLBACK_ON_RESERVED_CORES
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__ASSERT(cpu_count >= CONFIG_MP_MAX_NUM_CPUS,
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"The count of CPU Core nodes in dts is not greater or equal to CONFIG_MP_MAX_NUM_CPUS\n");
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#else
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__ASSERT(cpu_count == CONFIG_MP_MAX_NUM_CPUS,
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"The count of CPU Cores nodes in dts is not equal to CONFIG_MP_MAX_NUM_CPUS\n");
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for (i = 0, j = 0; i < cpu_count; i++) {
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if (cpu_node_list[i] == master_core_mpid) {
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continue;
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}
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if (j == cpu_num - 1) {
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cpu_mpid = cpu_node_list[i];
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break;
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}
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j++;
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}
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if (i == cpu_count) {
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printk("Can't find CPU Core %d from dts and failed to boot it\n", cpu_num);
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return;
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}
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#endif
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arm64_cpu_boot_params.sp = Z_KERNEL_STACK_BUFFER(stack) + sz;
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arm64_cpu_boot_params.fn = fn;
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arm64_cpu_boot_params.arg = arg;
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arm64_cpu_boot_params.cpu_num = cpu_num;
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barrier_dsync_fence_full();
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for (; i < cpu_count; i++) {
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if (cpu_node_list[i] == master_core_mpid) {
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continue;
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}
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/* store mpid last as this is our synchronization point */
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arm64_cpu_boot_params.mpid = cpu_mpid;
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cpu_mpid = cpu_node_list[i];
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sys_cache_data_invd_range((void *)&arm64_cpu_boot_params,
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sizeof(arm64_cpu_boot_params));
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barrier_dsync_fence_full();
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if (pm_cpu_on(cpu_mpid, (uint64_t)&__start)) {
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printk("Failed to boot secondary CPU core %d (MPID:%#llx)\n",
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cpu_num, cpu_mpid);
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return;
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/* store mpid last as this is our synchronization point */
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arm64_cpu_boot_params.mpid = cpu_mpid;
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sys_cache_data_invd_range((void *)&arm64_cpu_boot_params,
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sizeof(arm64_cpu_boot_params));
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if (pm_cpu_on(cpu_mpid, (uint64_t)&__start)) {
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printk("Failed to boot secondary CPU core %d (MPID:%#llx)\n",
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cpu_num, cpu_mpid);
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#ifdef CONFIG_ARM64_FALLBACK_ON_RESERVED_CORES
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printk("Falling back on reserved cores\n");
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continue;
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#else
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k_panic();
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#endif
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}
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break;
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}
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if (i++ == cpu_count) {
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printk("Can't find CPU Core %d from dts and failed to boot it\n", cpu_num);
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k_panic();
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}
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/* Wait secondary cores up, see z_arm64_secondary_start */
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