From f5ed5e6d0f40ca1e071f003d2edc687c42cd8901 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 1 Nov 2021 22:52:54 +0100 Subject: [PATCH] tests: drivers: pinctrl: gd32: add DT AF parse test Add a test to check that DT information for AF model is extracted correctly. Signed-off-by: Gerard Marull-Paretas --- tests/drivers/pinctrl/gd32/CMakeLists.txt | 12 ++ tests/drivers/pinctrl/gd32/Kconfig | 13 ++ .../gd32/boards/gd32f450i_eval.overlay | 63 +++++++++ tests/drivers/pinctrl/gd32/prj.conf | 5 + tests/drivers/pinctrl/gd32/src/main_af.c | 128 ++++++++++++++++++ tests/drivers/pinctrl/gd32/testcase.yaml | 7 + 6 files changed, 228 insertions(+) create mode 100644 tests/drivers/pinctrl/gd32/CMakeLists.txt create mode 100644 tests/drivers/pinctrl/gd32/Kconfig create mode 100644 tests/drivers/pinctrl/gd32/boards/gd32f450i_eval.overlay create mode 100644 tests/drivers/pinctrl/gd32/prj.conf create mode 100644 tests/drivers/pinctrl/gd32/src/main_af.c create mode 100644 tests/drivers/pinctrl/gd32/testcase.yaml diff --git a/tests/drivers/pinctrl/gd32/CMakeLists.txt b/tests/drivers/pinctrl/gd32/CMakeLists.txt new file mode 100644 index 00000000000..898ed03c804 --- /dev/null +++ b/tests/drivers/pinctrl/gd32/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2021 Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) + +project(pinctrl_gd32) + +target_sources(app PRIVATE ../common/test_device.c) +if(CONFIG_PINCTRL_GD32_AF) + target_sources(app PRIVATE src/main_af.c) +endif() diff --git a/tests/drivers/pinctrl/gd32/Kconfig b/tests/drivers/pinctrl/gd32/Kconfig new file mode 100644 index 00000000000..363b78eff64 --- /dev/null +++ b/tests/drivers/pinctrl/gd32/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021 Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +mainmenu "pinctrl GD32 DT Test" + +source "Kconfig.zephyr" + +config PINCTRL_TEST_NON_STATIC + bool "Enable access to pin control configuration" + select PINCTRL_NON_STATIC + help + This option should be selected by unit tests that need to access the pin + control configuration defined in a device driver. diff --git a/tests/drivers/pinctrl/gd32/boards/gd32f450i_eval.overlay b/tests/drivers/pinctrl/gd32/boards/gd32f450i_eval.overlay new file mode 100644 index 00000000000..361605f5d5d --- /dev/null +++ b/tests/drivers/pinctrl/gd32/boards/gd32f450i_eval.overlay @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2021 Teslabs Engineering S.L. + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + test_device: test_device { + compatible = "vnd,pinctrl-device"; + pinctrl-0 = <&test_device_default>; + pinctrl-names = "default"; + }; +}; + +&pinctrl { + test_device_default: test_device_default { + /* Note: the groups are just meant for testing if properties and + pins are parsed correctly, but do not necessarily represent a + feasible combination */ + pins1 { + pinmux = , + ; + }; + pins2 { + pinmux = ; + drive-push-pull; + }; + pins3 { + pinmux = ; + drive-open-drain; + }; + pins4 { + pinmux = ; + bias-disable; + }; + pins5 { + pinmux = ; + bias-pull-up; + }; + pins6 { + pinmux = ; + bias-pull-down; + }; + pins7 { + pinmux = ; + slew-rate = "max-speed-2mhz"; + }; + pins8 { + pinmux = ; + slew-rate = "max-speed-25mhz"; + }; + pins9 { + pinmux = ; + slew-rate = "max-speed-50mhz"; + }; + pins10 { + pinmux = ; + slew-rate = "max-speed-200mhz"; + }; + pins11 { + pinmux = ; + }; + }; +}; diff --git a/tests/drivers/pinctrl/gd32/prj.conf b/tests/drivers/pinctrl/gd32/prj.conf new file mode 100644 index 00000000000..bb844ad2efa --- /dev/null +++ b/tests/drivers/pinctrl/gd32/prj.conf @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ZTEST=y +CONFIG_PINCTRL_TEST_NON_STATIC=y diff --git a/tests/drivers/pinctrl/gd32/src/main_af.c b/tests/drivers/pinctrl/gd32/src/main_af.c new file mode 100644 index 00000000000..f38ed74c3b0 --- /dev/null +++ b/tests/drivers/pinctrl/gd32/src/main_af.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2021 Teslabs Engineering S.L. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/* pin configuration for test device */ +#define TEST_DEVICE DT_NODELABEL(test_device) +PINCTRL_DT_DEV_CONFIG_DECLARE(TEST_DEVICE); +static const struct pinctrl_dev_config *pcfg = PINCTRL_DT_DEV_CONFIG_GET(TEST_DEVICE); + +static void test_dt_extract(void) +{ + const struct pinctrl_state *scfg; + pinctrl_soc_pin_t pin; + + zassert_equal(pcfg->state_cnt, 1U, NULL); + + scfg = &pcfg->states[0]; + + zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT, NULL); + zassert_equal(scfg->pin_cnt, 12U, NULL); + + pin = scfg->pins[0]; + zassert_equal(GD32_PORT_GET(pin), 0, NULL); + zassert_equal(GD32_PIN_GET(pin), 0, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_AF0, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL); + + pin = scfg->pins[1]; + zassert_equal(GD32_PORT_GET(pin), 1, NULL); + zassert_equal(GD32_PIN_GET(pin), 1, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_AF1, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL); + + pin = scfg->pins[2]; + zassert_equal(GD32_PORT_GET(pin), 2, NULL); + zassert_equal(GD32_PIN_GET(pin), 2, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_AF2, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL); + + pin = scfg->pins[3]; + zassert_equal(GD32_PORT_GET(pin), 0, NULL); + zassert_equal(GD32_PIN_GET(pin), 3, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_AF3, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_OD, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL); + + pin = scfg->pins[4]; + zassert_equal(GD32_PORT_GET(pin), 1, NULL); + zassert_equal(GD32_PIN_GET(pin), 4, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_AF4, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL); + + pin = scfg->pins[5]; + zassert_equal(GD32_PORT_GET(pin), 2, NULL); + zassert_equal(GD32_PIN_GET(pin), 5, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_AF5, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_PULLUP, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL); + + pin = scfg->pins[6]; + zassert_equal(GD32_PORT_GET(pin), 0, NULL); + zassert_equal(GD32_PIN_GET(pin), 6, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_AF6, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_PULLDOWN, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL); + + pin = scfg->pins[7]; + zassert_equal(GD32_PORT_GET(pin), 1, NULL); + zassert_equal(GD32_PIN_GET(pin), 7, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_AF7, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL); + + pin = scfg->pins[8]; + zassert_equal(GD32_PORT_GET(pin), 2, NULL); + zassert_equal(GD32_PIN_GET(pin), 8, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_AF8, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_25MHZ, NULL); + + pin = scfg->pins[9]; + zassert_equal(GD32_PORT_GET(pin), 0, NULL); + zassert_equal(GD32_PIN_GET(pin), 9, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_AF9, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_50MHZ, NULL); + + pin = scfg->pins[10]; + zassert_equal(GD32_PORT_GET(pin), 1, NULL); + zassert_equal(GD32_PIN_GET(pin), 10, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_AF10, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_200MHZ, NULL); + + pin = scfg->pins[11]; + zassert_equal(GD32_PORT_GET(pin), 2, NULL); + zassert_equal(GD32_PIN_GET(pin), 11, NULL); + zassert_equal(GD32_AF_GET(pin), GD32_ANALOG, NULL); + zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL); + zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL); + zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL); +} + +void test_main(void) +{ + ztest_test_suite(pinctrl_gd32, + ztest_unit_test(test_dt_extract)); + ztest_run_test_suite(pinctrl_gd32); +} diff --git a/tests/drivers/pinctrl/gd32/testcase.yaml b/tests/drivers/pinctrl/gd32/testcase.yaml new file mode 100644 index 00000000000..881f9c963e2 --- /dev/null +++ b/tests/drivers/pinctrl/gd32/testcase.yaml @@ -0,0 +1,7 @@ +# Copyright (c) 2021 Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +tests: + drivers.pinctrl.gd32_af: + tags: drivers pinctrl + platform_allow: gd32f450i_eval