From f5ab199bb3a567d7cd5affe5dbb3570fd5b13c26 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 16 Aug 2024 11:13:27 -0500 Subject: [PATCH] soc: nxp_rw6xx: Do not enable unused clocks Update the clock init code to gate off unused clocks. Signed-off-by: Mahesh Mahadevan --- soc/nxp/rw/soc.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c index a936978995b..e3a54f26d38 100644 --- a/soc/nxp/rw/soc.c +++ b/soc/nxp/rw/soc.c @@ -67,12 +67,6 @@ __imx_boot_ivt_section void (*const image_vector_table[])(void) = { }; #endif /* CONFIG_NXP_RW6XX_BOOT_HEADER */ -const clock_avpll_config_t avpll_config = { - .ch1Freq = kCLOCK_AvPllChFreq12p288m, - .ch2Freq = kCLOCK_AvPllChFreq64m, - .enableCali = true -}; - /** * @brief Initialize the system clocks and peripheral clocks * @@ -95,8 +89,6 @@ __weak __ramfunc void clock_init(void) /* Initialize T3 clocks and t3pll_mci_48_60m_irc configured to 48.3MHz */ CLOCK_InitT3RefClk(kCLOCK_T3MciIrc48m); - /* Enable FFRO */ - CLOCK_EnableClock(kCLOCK_T3PllMciIrcClk); /* Enable T3 256M clock and SFRO */ CLOCK_EnableClock(kCLOCK_T3PllMci256mClk); @@ -114,17 +106,9 @@ __weak __ramfunc void clock_init(void) /* Enable tcpu_mci_clk 260MHz. Keep tcpu_mci_flexspi_clk gated. */ CLOCK_EnableClock(kCLOCK_TcpuMciClk); - /* tddr_mci_flexspi_clk 320MHz */ - CLOCK_InitTddrRefClk(kCLOCK_TddrFlexspiDiv10); - CLOCK_EnableClock(kCLOCK_TddrMciFlexspiClk); /* 320MHz */ - /* Enable AUX0 PLL to 260 MHz */ CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U); - /* Init AVPLL and enable both channels */ - CLOCK_InitAvPll(&avpll_config); - CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U); - /* Configure MainPll to 260MHz, then let CM33 run on Main PLL. */ CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1U); CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U); @@ -229,7 +213,17 @@ __weak __ramfunc void clock_init(void) #endif #endif /* CONFIG_SPI */ -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dmic0)) && CONFIG_AUDIO_DMIC_MCUX +#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dmic0)) && CONFIG_AUDIO_DMIC_MCUX) || CONFIG_I2S + const clock_avpll_config_t avpll_config = { + .ch1Freq = kCLOCK_AvPllChFreq12p288m, + .ch2Freq = kCLOCK_AvPllChFreq64m, + .enableCali = true + }; + + /* Init AVPLL and enable both channels */ + CLOCK_InitAvPll(&avpll_config); + CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U); + /* Clock DMIC from Audio PLL. PLL output is sourced from AVPLL * channel 1, which is clocked at 12.288 MHz. We can divide this * by 4 to achieve the desired DMIC bit clk of 3.072 MHz