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boards: st: n6: use hse as system source clock

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Use HSE as system source clock and adjust the different clock parameters
to use the highest admissible frequency (according to datasheet DS14791):
- CPU clock: 800MHz
- NPU clock: 1000MHz
- AXI clock: 800MHz
- AHB clock: 200MHz
Remove the setting of APB prescalers since they are constants set to 1.

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
Guillaume Gautier 2025-04-11 15:08:15 +02:00 • committed by Benjamin Cabé
commit f5a5dfcc43
2 changed files with 39 additions and 27 deletions
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28
boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi
View file

@ -68,9 +68,18 @@
}; };
&pll1 { &pll1 {
clocks = <&clk_hsi>; clocks = <&clk_hse>;
div-m = <4>; div-m = <3>;
mul-n = <75>; mul-n = <150>;
div-p1 = <1>;
div-p2 = <1>;
status = "okay";
};
&pll3 {
clocks = <&clk_hse>;
div-m = <3>;
mul-n = <125>;
div-p1 = <1>; div-p1 = <1>;
div-p2 = <1>; div-p2 = <1>;
status = "okay"; status = "okay";
@ -78,18 +87,18 @@
&ic1 { &ic1 {
pll-src = <1>; pll-src = <1>;
ic-div = <2>; ic-div = <3>;
status = "okay"; status = "okay";
}; };
&ic2 { &ic2 {
pll-src = <1>; pll-src = <1>;
ic-div = <3>; ic-div = <6>;
status = "okay"; status = "okay";
}; };
&ic6 { &ic6 {
pll-src = <1>; pll-src = <3>;
ic-div = <2>; ic-div = <2>;
status = "okay"; status = "okay";
}; };
@ -107,7 +116,7 @@
&cpusw { &cpusw {
clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>; clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
clock-frequency = <DT_FREQ_M(600)>; clock-frequency = <DT_FREQ_M(800)>;
status = "okay"; status = "okay";
}; };
@ -116,10 +125,7 @@
clocks = <&ic2>; clocks = <&ic2>;
clock-frequency = <DT_FREQ_M(400)>; clock-frequency = <DT_FREQ_M(400)>;
ahb-prescaler = <2>; ahb-prescaler = <2>;
apb1-prescaler = <1>; timg-prescaler = <2>;
apb2-prescaler = <1>;
apb4-prescaler = <1>;
apb5-prescaler = <1>;
}; };
&adc1 { &adc1 {

38
boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi
View file

@ -60,9 +60,9 @@
}; };
&pll1 { &pll1 {
clocks = <&clk_hsi>; clocks = <&clk_hse>;
div-m = <4>; div-m = <3>;
mul-n = <75>; mul-n = <150>;
div-p1 = <1>; div-p1 = <1>;
div-p2 = <1>; div-p2 = <1>;
status = "okay"; status = "okay";
@ -70,10 +70,19 @@
&pll2 { &pll2 {
clocks = <&clk_hsi>; clocks = <&clk_hsi>;
div-m = <4>; div-m = <2>;
mul-n = <24>; mul-n = <48>;
div-p1 = <2>; div-p1 = <1>;
div-p2 = <2>; div-p2 = <1>;
status = "okay";
};
&pll3 {
clocks = <&clk_hse>;
div-m = <3>;
mul-n = <125>;
div-p1 = <1>;
div-p2 = <1>;
status = "okay"; status = "okay";
}; };
@ -88,24 +97,24 @@
&ic1 { &ic1 {
pll-src = <1>; pll-src = <1>;
ic-div = <2>; ic-div = <3>;
status = "okay"; status = "okay";
}; };
&ic2 { &ic2 {
pll-src = <1>; pll-src = <1>;
ic-div = <3>; ic-div = <6>;
status = "okay"; status = "okay";
}; };
&ic4 { &ic4 {
pll-src = <2>; pll-src = <2>;
ic-div = <2>; ic-div = <32>;
status = "okay"; status = "okay";
}; };
&ic6 { &ic6 {
pll-src = <1>; pll-src = <3>;
ic-div = <2>; ic-div = <2>;
status = "okay"; status = "okay";
}; };
@ -129,7 +138,7 @@
&cpusw { &cpusw {
clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>; clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
clock-frequency = <DT_FREQ_M(600)>; clock-frequency = <DT_FREQ_M(800)>;
status = "okay"; status = "okay";
}; };
@ -138,10 +147,7 @@
clocks = <&ic2>; clocks = <&ic2>;
clock-frequency = <DT_FREQ_M(400)>; clock-frequency = <DT_FREQ_M(400)>;
ahb-prescaler = <2>; ahb-prescaler = <2>;
apb1-prescaler = <1>; timg-prescaler = <2>;
apb2-prescaler = <1>;
apb4-prescaler = <1>;
apb5-prescaler = <1>;
}; };
&adc1 { &adc1 {