From f596768427d6b4577b1f32a825201c2c7f5fc912 Mon Sep 17 00:00:00 2001
From: Andy Ross <andrew.j.ross@intel.com>
Date: Mon, 15 Feb 2021 19:59:18 -0800
Subject: [PATCH] soc/intel_adsp: Elevate cached/uncached mapping to a SoC API

The trace output layer was using this transformation already, make it
an official API.  There are other places doing similar logic that can
benefit.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
---
 .../intel_adsp/common/include/adsp/cache.h    | 44 +++++++++++++++++++
 soc/xtensa/intel_adsp/common/include/soc.h    |  1 +
 soc/xtensa/intel_adsp/common/trace_out.c      |  9 +---
 3 files changed, 47 insertions(+), 7 deletions(-)

diff --git a/soc/xtensa/intel_adsp/common/include/adsp/cache.h b/soc/xtensa/intel_adsp/common/include/adsp/cache.h
index 63075ab0b63..ea7c66f456b 100644
--- a/soc/xtensa/intel_adsp/common/include/adsp/cache.h
+++ b/soc/xtensa/intel_adsp/common/include/adsp/cache.h
@@ -15,4 +15,48 @@
 #define SOC_DCACHE_INVALIDATE(addr, size)	\
 	xthal_dcache_region_invalidate((addr), (size))
 
+/**
+ * @brief Return uncached pointer to a RAM address
+ *
+ * The Intel ADSP architecture maps all addressable RAM (of all types)
+ * twice, in two different 512MB segments regions whose L1 cache
+ * settings can be controlled independently.  So for any given
+ * pointer, it is possible to convert it to and from a cached version.
+ *
+ * This function takes a pointer to any addressible object (either in
+ * cacheable memory or not) and returns a pointer that can be used to
+ * refer to the same memory while bypassing the L1 data cache.  Data
+ * in the L1 cache will not be inspected nor modified by the access.
+ *
+ * @see z_soc_cached_ptr()
+ *
+ * @param p A pointer to a valid C object
+ * @return A pointer to the same object bypassing the L1 dcache
+ */
+static inline void *z_soc_uncached_ptr(void *p)
+{
+	return ((void *)(((size_t)p) & ~0x20000000));
+}
+
+/**
+ * @brief Return cached pointer to a RAM address
+ *
+ * This function takes a pointer to any addressible object (either in
+ * cacheable memory or not) and returns a pointer that can be used to
+ * refer to the same memory through the L1 data cache.  Data read
+ * through the resulting pointer will reflect locally cached values on
+ * the current CPU if they exist, and writes will go first into the
+ * cache and be written back later.
+ *
+ * @see z_soc_uncached_ptr()
+ *
+ * @param p A pointer to a valid C object
+ * @return A pointer to the same object via the L1 dcache
+
+ */
+static inline void *z_soc_cached_ptr(void *p)
+{
+	return ((void *)(((size_t)p) | 0x20000000));
+}
+
 #endif
diff --git a/soc/xtensa/intel_adsp/common/include/soc.h b/soc/xtensa/intel_adsp/common/include/soc.h
index 4fc9b6c7df0..63dae0c6765 100644
--- a/soc/xtensa/intel_adsp/common/include/soc.h
+++ b/soc/xtensa/intel_adsp/common/include/soc.h
@@ -167,4 +167,5 @@ extern void z_soc_irq_enable(uint32_t irq);
 extern void z_soc_irq_disable(uint32_t irq);
 extern int z_soc_irq_is_enabled(unsigned int irq);
 
+
 #endif /* __INC_SOC_H */
diff --git a/soc/xtensa/intel_adsp/common/trace_out.c b/soc/xtensa/intel_adsp/common/trace_out.c
index 4edc18cacb6..9df11067c09 100644
--- a/soc/xtensa/intel_adsp/common/trace_out.c
+++ b/soc/xtensa/intel_adsp/common/trace_out.c
@@ -28,11 +28,6 @@
 #define NSLOTS (SRAM_TRACE_SIZE / SLOT_SIZE)
 #define MSGSZ (SLOT_SIZE - sizeof(struct slot_hdr))
 
-/* Translates a SRAM pointer into an address of the same memory in the
- * uncached region from 0x80000000-0x9fffffff
- */
-#define UNCACHED_PTR(p) ((void *)(((int)p) & ~0x20000000))
-
 struct slot_hdr {
 	uint16_t magic;
 	uint16_t id;
@@ -56,11 +51,11 @@ static __aligned(64) union {
 	uint32_t cache_pad[16];
 } data_rec;
 
-#define data ((volatile struct metadata *)UNCACHED_PTR(&data_rec.meta))
+#define data ((volatile struct metadata *)z_soc_uncached_ptr(&data_rec.meta))
 
 static inline struct slot *slot(int i)
 {
-	struct slot *slots = UNCACHED_PTR(SRAM_TRACE_BASE);
+	struct slot *slots = z_soc_uncached_ptr((void *)SRAM_TRACE_BASE);
 
 	return &slots[i];
 }