arm: v2m_musca: Enable GPIO support

Enable CMSDK GPIO driver on v2m_musca SoC/Board.  Add LEDs that are on
the board and init the pinmux for those LEDs to work.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2019-09-17 13:33:56 -05:00 committed by Kumar Gala
commit f54ab8c4fb
6 changed files with 62 additions and 0 deletions

View file

@ -21,6 +21,15 @@ config BOARD
endif
if GPIO
config GPIO_CMSDK_AHB
default y
config GPIO_CMSDK_AHB_PORT0
default y
endif
if SERIAL

View file

@ -22,6 +22,10 @@
#define IOMUX_ALTF1_OUTSEL (0x44 >> 2)
#define IOMUX_ALTF1_OENSEL (0x48 >> 2)
#define IOMUX_ALTF1_DEFAULT_IN (0x4c >> 2)
#define IOMUX_ALTF2_INSEL (0x50 >> 2)
#define IOMUX_ALTF2_OUTSEL (0x54 >> 2)
#define IOMUX_ALTF2_OENSEL (0x58 >> 2)
#define IOMUX_ALTF2_DEFAULT_IN (0x5c >> 2)
#ifdef CONFIG_TRUSTED_EXECUTION_SECURE
/*
@ -47,6 +51,13 @@ static void arm_musca_pinmux_defaults(void)
#else
static void arm_musca_pinmux_defaults(void)
{
volatile u32_t *scc = (u32_t *)DT_ARM_SCC_BASE_ADDRESS;
/* Enable PINs for LEDS */
scc[IOMUX_ALTF1_OUTSEL] &= ~(BIT(2) | BIT(3) | BIT(4));
scc[IOMUX_ALTF1_OENSEL] &= ~(BIT(2) | BIT(3) | BIT(4));
scc[IOMUX_ALTF2_OUTSEL] &= ~(BIT(2) | BIT(3) | BIT(4));
scc[IOMUX_ALTF2_OENSEL] &= ~(BIT(2) | BIT(3) | BIT(4));
}
#endif

View file

@ -69,3 +69,15 @@ scc@10c000 {
compatible = "arm,scc";
reg = <0x10c000 0x1000>;
};
gpio: gpio@110000 {
compatible = "arm,cmsdk-gpio";
reg = <0x110000 0x1000>;
interrupts = <51 3 52 3 53 3 54 3
55 3 56 3 57 3 58 3
59 3 60 3 61 3 62 3
63 3 64 3 65 3 66 3>;
gpio-controller;
#gpio-cells = <2>;
label = "GPIO_0";
};

View file

@ -13,6 +13,12 @@
#address-cells = <1>;
#size-cells = <1>;
aliases {
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
};
chosen {
zephyr,console = &uart1;
zephyr,sram = &sram0;
@ -20,6 +26,21 @@
zephyr,shell-uart = &uart1;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpio 2 0>;
label = "User LD1";
};
green_led: led_1 {
gpios = <&gpio 3 0>;
label = "User LD2";
};
blue_led: led_2 {
gpios = <&gpio 4 0>;
label = "User LD3";
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;

View file

@ -8,3 +8,4 @@ toolchain:
- zephyr
supported:
- counter
- gpio

View file

@ -36,6 +36,10 @@
/* SCC */
#define DT_ARM_SCC_BASE_ADDRESS DT_ARM_SCC_4010C000_BASE_ADDRESS
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40110000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40110000_IRQ_0
#else
/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
@ -62,6 +66,10 @@
/* SCC */
#define DT_ARM_SCC_BASE_ADDRESS DT_ARM_SCC_5010C000_BASE_ADDRESS
/* CMSDK AHB General Purpose Input/Output (GPIO) */
#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_50110000_BASE_ADDRESS
#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_50110000_IRQ_0
#endif
/* End of SoC Level DTS fixup file */