arm: v2m_musca: Enable GPIO support
Enable CMSDK GPIO driver on v2m_musca SoC/Board. Add LEDs that are on the board and init the pinmux for those LEDs to work. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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6 changed files with 62 additions and 0 deletions
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@ -21,6 +21,15 @@ config BOARD
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endif
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if GPIO
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config GPIO_CMSDK_AHB
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default y
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config GPIO_CMSDK_AHB_PORT0
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default y
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endif
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if SERIAL
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@ -22,6 +22,10 @@
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#define IOMUX_ALTF1_OUTSEL (0x44 >> 2)
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#define IOMUX_ALTF1_OENSEL (0x48 >> 2)
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#define IOMUX_ALTF1_DEFAULT_IN (0x4c >> 2)
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#define IOMUX_ALTF2_INSEL (0x50 >> 2)
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#define IOMUX_ALTF2_OUTSEL (0x54 >> 2)
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#define IOMUX_ALTF2_OENSEL (0x58 >> 2)
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#define IOMUX_ALTF2_DEFAULT_IN (0x5c >> 2)
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#ifdef CONFIG_TRUSTED_EXECUTION_SECURE
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/*
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@ -47,6 +51,13 @@ static void arm_musca_pinmux_defaults(void)
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#else
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static void arm_musca_pinmux_defaults(void)
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{
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volatile u32_t *scc = (u32_t *)DT_ARM_SCC_BASE_ADDRESS;
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/* Enable PINs for LEDS */
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scc[IOMUX_ALTF1_OUTSEL] &= ~(BIT(2) | BIT(3) | BIT(4));
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scc[IOMUX_ALTF1_OENSEL] &= ~(BIT(2) | BIT(3) | BIT(4));
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scc[IOMUX_ALTF2_OUTSEL] &= ~(BIT(2) | BIT(3) | BIT(4));
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scc[IOMUX_ALTF2_OENSEL] &= ~(BIT(2) | BIT(3) | BIT(4));
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}
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#endif
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@ -69,3 +69,15 @@ scc@10c000 {
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compatible = "arm,scc";
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reg = <0x10c000 0x1000>;
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};
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gpio: gpio@110000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x110000 0x1000>;
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interrupts = <51 3 52 3 53 3 54 3
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55 3 56 3 57 3 58 3
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59 3 60 3 61 3 62 3
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63 3 64 3 65 3 66 3>;
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gpio-controller;
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#gpio-cells = <2>;
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label = "GPIO_0";
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};
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@ -13,6 +13,12 @@
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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led0 = &green_led;
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led1 = &blue_led;
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led2 = &red_led;
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};
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chosen {
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zephyr,console = &uart1;
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zephyr,sram = &sram0;
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@ -20,6 +26,21 @@
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zephyr,shell-uart = &uart1;
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};
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leds {
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compatible = "gpio-leds";
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red_led: led_0 {
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gpios = <&gpio 2 0>;
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label = "User LD1";
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};
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green_led: led_1 {
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gpios = <&gpio 3 0>;
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label = "User LD2";
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};
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blue_led: led_2 {
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gpios = <&gpio 4 0>;
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label = "User LD3";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -8,3 +8,4 @@ toolchain:
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- zephyr
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supported:
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- counter
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- gpio
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@ -36,6 +36,10 @@
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/* SCC */
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#define DT_ARM_SCC_BASE_ADDRESS DT_ARM_SCC_4010C000_BASE_ADDRESS
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/* CMSDK AHB General Purpose Input/Output (GPIO) */
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#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40110000_BASE_ADDRESS
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#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40110000_IRQ_0
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#else
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/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
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@ -62,6 +66,10 @@
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/* SCC */
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#define DT_ARM_SCC_BASE_ADDRESS DT_ARM_SCC_5010C000_BASE_ADDRESS
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/* CMSDK AHB General Purpose Input/Output (GPIO) */
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#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_50110000_BASE_ADDRESS
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#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_50110000_IRQ_0
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#endif
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/* End of SoC Level DTS fixup file */
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