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soc: nxp: move init code from SYS_INIT to hooks

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Replace SYS_INIT with SoC hooks and adapt SoC init code

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2024-09-10 09:42:40 -04:00 • committed by Henrik Brix Andersen
commit f519f00f16
50 changed files with 73 additions and 158 deletions
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1
soc/nxp/imx/imx6sx/Kconfig
View file

@ -9,6 +9,7 @@ config SOC_SERIES_IMX6SX
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select CLOCK_CONTROL
select SOC_EARLY_INIT_HOOK
config SOC_MCIMX6X_M4
select HAS_IMX_HAL

6
soc/nxp/imx/imx6sx/soc.c
View file

@ -287,7 +287,7 @@ static void SOC_ClockInit(void)
*
* @return 0
*/
static int mcimx6x_m4_init(void)
void soc_early_init_hook(void)
{
/* Configure RDC */
SOC_RdcInit();
@ -300,8 +300,4 @@ static int mcimx6x_m4_init(void)
/* Initialize clock */
SOC_ClockInit();
return 0;
}
SYS_INIT(mcimx6x_m4_init, PRE_KERNEL_1, 0);

1
soc/nxp/imx/imx7d/Kconfig
View file

@ -8,6 +8,7 @@ config SOC_SERIES_IMX7D
select CLOCK_CONTROL
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select SOC_EARLY_INIT_HOOK
config SOC_MCIMX7D_M4
select HAS_IMX_HAL

6
soc/nxp/imx/imx7d/soc.c
View file

@ -222,7 +222,7 @@ static void nxp_mcimx7_mu_config(void)
}
#endif /* CONFIG_IPM_IMX */
static int nxp_mcimx7_init(void)
void soc_early_init_hook(void)
{
/* SoC specific RDC settings */
@ -250,8 +250,4 @@ static int nxp_mcimx7_init(void)
#ifdef CONFIG_IPM_IMX
nxp_mcimx7_mu_config();
#endif /* CONFIG_IPM_IMX */
return 0;
}
SYS_INIT(nxp_mcimx7_init, PRE_KERNEL_1, 0);

5
soc/nxp/imx/imx8m/Kconfig
View file

@ -10,6 +10,7 @@ config SOC_MIMX8MM6_A53
select HAS_MCUX_IOMUXC if PINCTRL
select HAS_MCUX_RDC
select HAS_MCUX_CACHE
select SOC_PREP_HOOK
config SOC_MIMX8MM6_M4
select ARM
@ -21,6 +22,7 @@ config SOC_MIMX8MM6_M4
select HAS_MCUX_RDC
select HAS_MCUX_IGPIO
select HAS_MCUX_IOMUXC
select SOC_EARLY_INIT_HOOK
config SOC_MIMX8ML8_A53
select ARM64
@ -31,6 +33,7 @@ config SOC_MIMX8ML8_A53
select HAS_MCUX_IOMUXC if PINCTRL
select HAS_MCUX_RDC
select HAS_MCUX_CACHE
select SOC_PREP_HOOK
config SOC_MIMX8MN6_A53
select ARM64
@ -41,6 +44,7 @@ config SOC_MIMX8MN6_A53
select HAS_MCUX_IOMUXC if PINCTRL
select HAS_MCUX_RDC
select HAS_MCUX_CACHE
select SOC_PREP_HOOK
config SOC_MIMX8ML8_ADSP
select XTENSA
@ -71,6 +75,7 @@ config SOC_MIMX8ML8_M7
select ARM_MPU
select HAS_MCUX_IGPIO
select HAS_MCUX_IOMUXC
select SOC_EARLY_INIT_HOOK
config SOC_MIMX8MQ6_M4
select ARM

6
soc/nxp/imx/imx8m/a53/soc.c
View file

@ -52,11 +52,7 @@ static void soc_rdc_init(void)
#endif
static int soc_init(void)
void soc_prep_hook(void)
{
soc_rdc_init();
return 0;
}
SYS_INIT(soc_init, EARLY, 1);

6
soc/nxp/imx/imx8m/m4_mini/soc.c
View file

@ -148,7 +148,7 @@ static void SOC_ClockInit(void)
CLOCK_EnableClock(kCLOCK_Sec_Debug);
}
static int nxp_mimx8mm6_init(void)
void soc_early_init_hook(void)
{
/* SoC specific RDC settings */
@ -156,8 +156,4 @@ static int nxp_mimx8mm6_init(void)
/* SoC specific Clock settings */
SOC_ClockInit();
return 0;
}
SYS_INIT(nxp_mimx8mm6_init, PRE_KERNEL_1, 0);

6
soc/nxp/imx/imx8m/m4_quad/soc.c
View file

@ -111,7 +111,7 @@ static void SOC_ClockInit(void)
CLOCK_EnableClock(kCLOCK_Sec_Debug);
}
static int nxp_mimx8mq6_init(void)
void soc_early_init_hook(void)
{
/* SoC specific RDC settings */
@ -119,8 +119,4 @@ static int nxp_mimx8mq6_init(void)
/* SoC specific Clock settings */
SOC_ClockInit();
return 0;
}
SYS_INIT(nxp_mimx8mq6_init, PRE_KERNEL_1, 0);

6
soc/nxp/imx/imx8m/m7/soc.c
View file

@ -203,7 +203,7 @@ static void gpio_init(void)
#endif
}
static int nxp_mimx8ml8_init(void)
void soc_early_init_hook(void)
{
/* SoC specific RDC settings */
@ -213,8 +213,4 @@ static int nxp_mimx8ml8_init(void)
SOC_ClockInit();
gpio_init();
return 0;
}
SYS_INIT(nxp_mimx8ml8_init, PRE_KERNEL_1, 0);

3
soc/nxp/imxrt/imxrt10xx/Kconfig
View file

@ -6,7 +6,6 @@ config SOC_SERIES_IMXRT10XX
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select SOC_RESET_HOOK
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
select ARM
select CLOCK_CONTROL
@ -29,6 +28,8 @@ config SOC_SERIES_IMXRT10XX
select HAS_MCUX_USB_EHCI
select HAS_SWO
select HAS_PM
select SOC_RESET_HOOK
select SOC_EARLY_INIT_HOOK
config SOC_MIMXRT1011
select CPU_HAS_FPU

6
soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c
View file

@ -339,7 +339,7 @@ void clock_lpm_init(void)
XTALOSC24M->OSC_CONFIG1 = tmp_reg;
}
static int imxrt_lpm_init(void)
void imxrt_lpm_init(void)
{
struct clock_callbacks callbacks;
@ -464,8 +464,4 @@ static int imxrt_lpm_init(void)
/* Install LPM callbacks */
imxrt_clock_pm_callbacks_register(&callbacks);
return 0;
}
SYS_INIT(imxrt_lpm_init, PRE_KERNEL_1, 0);

7
soc/nxp/imxrt/imxrt10xx/power.c
View file

@ -240,7 +240,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
}
/* Initialize power system */
static int rt10xx_power_init(void)
void rt10xx_power_init(void)
{
dcdc_internal_regulator_config_t reg_config;
@ -268,9 +268,4 @@ static int rt10xx_power_init(void)
/* Enable high gate drive on power FETs to reduce leakage current */
PMU_CoreEnableIncreaseGateDrive(PMU, true);
return 0;
}
SYS_INIT(rt10xx_power_init, PRE_KERNEL_2, 0);

18
soc/nxp/imxrt/imxrt10xx/soc.c
View file

@ -332,25 +332,29 @@ void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src,
}
#endif
extern void rt10xx_power_init(void);
extern void imxrt_lpm_init(void);
/**
*
* @brief Perform basic hardware initialization
*
* Initialize the interrupt controller device drivers.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
static int imxrt_init(void)
void soc_early_init_hook(void)
{
sys_cache_instr_enable();
sys_cache_data_enable();
/* Initialize system clock */
clock_init();
return 0;
#ifdef CONFIG_PM
#ifdef CONFIG_SOC_MIMXRT1064
imxrt_lpm_init();
#endif
rt10xx_power_init();
#endif
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -365,5 +369,3 @@ void soc_reset_hook(void)
#endif
}
#endif
SYS_INIT(imxrt_init, PRE_KERNEL_1, 0);

1
soc/nxp/imxrt/imxrt118x/Kconfig
View file

@ -21,6 +21,7 @@ config SOC_SERIES_IMXRT118X
select HAS_MCUX_IOMUXC
select HAS_SWO
select HAS_MCUX_FLEXSPI
select SOC_EARLY_INIT_HOOK
config SOC_MIMXRT1189_CM33
select CPU_CORTEX_M33

6
soc/nxp/imxrt/imxrt118x/soc.c
View file

@ -394,7 +394,7 @@ static ALWAYS_INLINE void trdc_enable_all_access(void)
* @return 0
*/
static int imxrt_init(void)
void soc_early_init_hook(void)
{
/* Initialize system clock */
clock_init();
@ -409,8 +409,6 @@ static int imxrt_init(void)
#endif
__ISB();
__DSB();
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -419,5 +417,3 @@ void soc_reset_hook(void)
SystemInit();
}
#endif
SYS_INIT(imxrt_init, PRE_KERNEL_1, 0);

1
soc/nxp/imxrt/imxrt5xx/Kconfig
View file

@ -31,6 +31,7 @@ config SOC_MIMXRT595S_CM33
select HAS_MCUX_USDHC2
select HAS_MCUX_USB_LPCIP3511
select HAS_MCUX_CTIMER
select SOC_EARLY_INIT_HOOK
config SOC_MIMXRT595S_F1
select XTENSA

7
soc/nxp/imxrt/imxrt5xx/cm33/power.c
View file

@ -61,10 +61,8 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
}
/* Initialize power system */
static int rt5xx_power_init(void)
void rt5xx_power_init(void)
{
int ret = 0;
/* This function is called to set vddcore low voltage detection
* falling trip voltage, this is not impacting the voltage in anyway.
*/
@ -75,7 +73,4 @@ static int rt5xx_power_init(void)
POWER_UpdatePmicRecoveryTime(1);
#endif
return ret;
}
SYS_INIT(rt5xx_power_init, PRE_KERNEL_2, 0);

12
soc/nxp/imxrt/imxrt5xx/cm33/soc.c
View file

@ -511,16 +511,16 @@ void __weak imxrt_deinit_display_interface(void)
#endif
extern void rt5xx_power_init(void);
/**
*
* @brief Perform basic hardware initialization
*
* Initialize the interrupt controller device drivers.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
static int nxp_rt500_init(void)
void soc_early_init_hook(void)
{
/* Initialize clocks with tool generated code */
rt5xx_clock_init();
@ -536,8 +536,8 @@ static int nxp_rt500_init(void)
IOPCTL->PIO[1][15] = 0;
IOPCTL->PIO[3][28] = 0;
IOPCTL->PIO[3][29] = 0;
#ifdef CONFIG_PM
rt5xx_power_init();
#endif
return 0;
}
SYS_INIT(nxp_rt500_init, PRE_KERNEL_1, 0);

1
soc/nxp/imxrt/imxrt6xx/Kconfig
View file

@ -30,6 +30,7 @@ config SOC_MIMXRT685S_CM33
select INIT_SYS_PLL
select HAS_MCUX_USB_LPCIP3511
select HAS_MCUX_CTIMER
select SOC_EARLY_INIT_HOOK
if SOC_SERIES_IMXRT6XX

8
soc/nxp/imxrt/imxrt6xx/cm33/soc.c
View file

@ -360,11 +360,9 @@ void imxrt_usdhc_dat3_pull(bool pullup)
*
* Initialize the interrupt controller device drivers.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
static int nxp_rt600_init(void)
void soc_early_init_hook(void)
{
/* Initialize clock */
clock_init();
@ -372,8 +370,6 @@ static int nxp_rt600_init(void)
#ifndef CONFIG_IMXRT6XX_CODE_CACHE
CACHE64_DisableCache(CACHE64);
#endif
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -400,5 +396,3 @@ void soc_reset_hook(void)
}
#endif
SYS_INIT(nxp_rt600_init, PRE_KERNEL_1, 0);

1
soc/nxp/kinetis/k2x/Kconfig
View file

@ -14,6 +14,7 @@ config SOC_SERIES_KINETIS_K2X
select CPU_CORTEX_M_HAS_DWT
select CLOCK_CONTROL
select SOC_RESET_HOOK
select SOC_EARLY_INIT_HOOK
config SOC_MK22F51212
select HAS_MCUX

6
soc/nxp/kinetis/k2x/soc.c
View file

@ -118,15 +118,13 @@ static ALWAYS_INLINE void clock_init(void)
* @return 0
*/
static int fsl_frdm_k22f_init(void)
void soc_early_init_hook(void)
{
/* release I/O power hold to allow normal run state */
PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
/* Initialize PLL/system clock to 120 MHz */
clock_init();
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -137,5 +135,3 @@ void soc_reset_hook(void)
}
#endif /* CONFIG_SOC_RESET_HOOK */
SYS_INIT(fsl_frdm_k22f_init, PRE_KERNEL_1, 0);

1
soc/nxp/kinetis/k6x/Kconfig
View file

@ -11,6 +11,7 @@ config SOC_SERIES_KINETIS_K6X
select HAS_MCUX_PIT
select CLOCK_CONTROL
select SOC_RESET_HOOK
select SOC_EARLY_INIT_HOOK
config SOC_MK64F12
select HAS_MCUX

7
soc/nxp/kinetis/k6x/soc.c
View file

@ -124,10 +124,9 @@ static ALWAYS_INLINE void clock_init(void)
* Initialize the interrupt controller device drivers.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
static int k6x_init(void)
void soc_early_init_hook(void)
{
#if !defined(CONFIG_ARM_MPU)
uint32_t temp_reg;
@ -162,8 +161,6 @@ static int k6x_init(void)
#endif
/* Initialize PLL/system clock up to 180 MHz */
clock_init();
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -174,5 +171,3 @@ void soc_reset_hook(void)
}
#endif /* CONFIG_SOC_RESET_HOOK */
SYS_INIT(k6x_init, PRE_KERNEL_1, 0);

1
soc/nxp/kinetis/k8x/Kconfig
View file

@ -27,6 +27,7 @@ config SOC_SERIES_KINETIS_K8X
select HAS_MCUX_RCM
select HAS_MCUX_CACHE
select SOC_RESET_HOOK
select SOC_EARLY_INIT_HOOK
if SOC_SERIES_KINETIS_K8X

6
soc/nxp/kinetis/k8x/soc.c
View file

@ -92,7 +92,7 @@ static ALWAYS_INLINE void clk_init(void)
#endif
}
static int k8x_init(void)
void soc_early_init_hook(void)
{
#if !defined(CONFIG_ARM_MPU)
uint32_t temp_reg;
@ -116,8 +116,6 @@ static int k8x_init(void)
/* Initialize system clocks and PLL */
clk_init();
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -128,5 +126,3 @@ void soc_reset_hook(void)
}
#endif /* CONFIG_SOC_RESET_HOOK */
SYS_INIT(k8x_init, PRE_KERNEL_1, 0);

1
soc/nxp/kinetis/ke1xf/Kconfig
View file

@ -30,6 +30,7 @@ config SOC_SERIES_KINETIS_KE1XF
select HAS_MCUX_PWT
select HAS_MCUX_RCM
select SOC_RESET_HOOK
select SOC_EARLY_INIT_HOOK
select HAS_PM
config SOC_MKE16F16

6
soc/nxp/kinetis/ke1xf/soc.c
View file

@ -237,7 +237,7 @@ static ALWAYS_INLINE void clk_init(void)
#endif
}
static int ke1xf_init(void)
void soc_early_init_hook(void)
{
#if !defined(CONFIG_ARM_MPU)
@ -264,8 +264,6 @@ static int ke1xf_init(void)
/* SystemInit will have enabled the code cache. Disable it here */
L1CACHE_DisableCodeCache();
#endif
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -314,5 +312,3 @@ void soc_reset_hook(void)
}
#endif /* CONFIG_SOC_RESET_HOOK */
SYS_INIT(ke1xf_init, PRE_KERNEL_1, 0);

1
soc/nxp/kinetis/ke1xz/Kconfig
View file

@ -13,3 +13,4 @@ config SOC_SERIES_KE1XZ
select HAS_MCUX
select HAS_PM
select SOC_RESET_HOOK
select SOC_EARLY_INIT_HOOK

6
soc/nxp/kinetis/ke1xz/soc.c
View file

@ -144,13 +144,11 @@ static ALWAYS_INLINE void clk_init(void)
#endif
}
static int ke1xz_init(void)
void soc_early_init_hook(void)
{
/* Initialize system clocks and PLL */
clk_init();
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -162,5 +160,3 @@ void soc_reset_hook(void)
}
#endif /* CONFIG_SOC_RESET_HOOK */
SYS_INIT(ke1xz_init, PRE_KERNEL_1, 0);

1
soc/nxp/kinetis/kl2x/Kconfig
View file

@ -10,6 +10,7 @@ config SOC_SERIES_KINETIS_KL2X
select CPU_CORTEX_M_HAS_VTOR
select CLOCK_CONTROL
select SOC_RESET_HOOK
select SOC_EARLY_INIT_HOOK
config SOC_MKL25Z4
select CPU_CORTEX_M0PLUS

6
soc/nxp/kinetis/kl2x/soc.c
View file

@ -79,12 +79,10 @@ static ALWAYS_INLINE void clock_init(void)
#endif
}
static int kl2x_init(void)
void soc_early_init_hook(void)
{
/* Initialize system clock to 48 MHz */
clock_init();
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -95,5 +93,3 @@ void soc_reset_hook(void)
}
#endif /* CONFIG_SOC_RESET_HOOK */
SYS_INIT(kl2x_init, PRE_KERNEL_1, 0);

1
soc/nxp/kinetis/kv5x/Kconfig
View file

@ -22,3 +22,4 @@ config SOC_SERIES_KINETIS_KV5X
select HAS_MCG
select HAS_MCUX_RCM
select SOC_RESET_HOOK
select SOC_EARLY_INIT_HOOK

6
soc/nxp/kinetis/kv5x/soc.c
View file

@ -78,7 +78,7 @@ static ALWAYS_INLINE void clk_init(void)
CLOCK_SetSimConfig(&sim_config);
}
static int kv5x_init(void)
void soc_early_init_hook(void)
{
/* release I/O power hold to allow normal run state */
PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
@ -93,8 +93,6 @@ static int kv5x_init(void)
sys_cache_instr_enable();
sys_cache_data_enable();
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -105,5 +103,3 @@ void soc_reset_hook(void)
}
#endif /* CONFIG_SOC_RESET_HOOK */
SYS_INIT(kv5x_init, PRE_KERNEL_1, 0);

1
soc/nxp/kinetis/kwx/Kconfig
View file

@ -9,6 +9,7 @@ config SOC_SERIES_KINETIS_KWX
select CPU_CORTEX_M_HAS_VTOR
select CLOCK_CONTROL
select SOC_RESET_HOOK
select SOC_EARLY_INIT_HOOK
config SOC_MKW22D5
select CPU_CORTEX_M4

6
soc/nxp/kinetis/kwx/soc_kw2xd.c
View file

@ -147,15 +147,13 @@ static ALWAYS_INLINE void clock_init(void)
*
* @return 0
*/
static int kw2xd_init(void)
void soc_early_init_hook(void)
{
/* release I/O power hold to allow normal run state */
PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
/* Initialize PLL/system clock to 48 MHz */
clock_init();
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -166,5 +164,3 @@ void soc_reset_hook(void)
}
#endif /* CONFIG_SOC_RESET_HOOK */
SYS_INIT(kw2xd_init, PRE_KERNEL_1, 0);

6
soc/nxp/kinetis/kwx/soc_kw4xz.c
View file

@ -79,12 +79,10 @@ static ALWAYS_INLINE void clock_init(void)
#endif
}
static int kwx_init(void)
void soc_early_init_hook(void)
{
/* Initialize system clock to 40 MHz */
clock_init();
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -95,5 +93,3 @@ void soc_reset_hook(void)
}
#endif /* CONFIG_SOC_RESET_HOOK */
SYS_INIT(kwx_init, PRE_KERNEL_1, 0);

1
soc/nxp/lpc/lpc51u68/Kconfig
View file

@ -16,6 +16,7 @@ config SOC_SERIES_LPC51U68
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select SOC_RESET_HOOK
select SOC_EARLY_INIT_HOOK
config SOC_LPC51U68
select CLOCK_CONTROL

8
soc/nxp/lpc/lpc51u68/soc.c
View file

@ -11,7 +11,7 @@
#include <fsl_power.h>
#include <fsl_clock.h>
int soc_init(void)
void soc_early_init_hook(void)
{
POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);
CLOCK_SetupFROClocking(12000000U);
@ -42,17 +42,11 @@ int soc_init(void)
POWER_DisablePD(kPDRUNCFG_PD_VD7_ENA);
POWER_DisablePD(kPDRUNCFG_PD_VREFP_SW);
POWER_DisablePD(kPDRUNCFG_PD_TEMPS);
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
void soc_reset_hook(void)
{
SystemInit();
}
#endif /* CONFIG_SOC_RESET_HOOK */
SYS_INIT(soc_init, PRE_KERNEL_1, 0);

1
soc/nxp/mcx/mcxc/Kconfig
View file

@ -16,6 +16,7 @@ config SOC_SERIES_MCXC
select HAS_MCUX_LPUART
select HAS_MCUX_LPI2C
select HAS_MCUX_TPM
select SOC_EARLY_INIT_HOOK
if SOC_SERIES_MCXC

5
soc/nxp/mcx/mcxc/soc.c
View file

@ -107,10 +107,9 @@ static void clock_init(void)
#endif
}
static int mcxc_init(void)
void soc_early_init_hook(void)
{
clock_init();
return 0;
}
#ifdef CONFIG_SOC_RESET_HOOK
@ -121,5 +120,3 @@ void soc_reset_hook(void)
}
#endif /* CONFIG_SOC_RESET_HOOK */
SYS_INIT(mcxc_init, PRE_KERNEL_1, 0);

1
soc/nxp/rw/Kconfig
View file

@ -17,6 +17,7 @@ config SOC_SERIES_RW6XX
select HAS_MCUX_FLEXCOMM
select HAS_MCUX_CACHE
select HAS_PM
select SOC_EARLY_INIT_HOOK
if SOC_SERIES_RW6XX

6
soc/nxp/rw/power.c
View file

@ -109,7 +109,7 @@ __weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
__enable_irq();
}
static int nxp_rw6xx_power_init(void)
void nxp_rw6xx_power_init(void)
{
uint32_t suspend_sleepconfig[5] = DT_PROP_OR(NODE_ID, deep_sleep_config, {});
@ -142,8 +142,4 @@ static int nxp_rw6xx_power_init(void)
IRQ_CONNECT(DT_IRQN(DT_NODELABEL(pin1)), DT_IRQ(DT_NODELABEL(pin1), priority), pin1_isr,
NULL, 0);
#endif
return 0;
}
SYS_INIT(nxp_rw6xx_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

12
soc/nxp/rw/soc.c
View file

@ -268,17 +268,16 @@ __ramfunc void clock_init(void)
}
extern void nxp_rw6xx_power_init(void);
/**
*
* @brief Perform basic hardware initialization
*
* Initialize the interrupt controller device drivers.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
static int nxp_rw600_init(void)
void soc_early_init_hook(void)
{
#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt), nxp_lpc_wwdt, okay))
POWER_EnableResetSource(kPOWER_ResetSourceWdt);
@ -305,8 +304,9 @@ static int nxp_rw600_init(void)
#if defined(CONFIG_ADC_MCUX_GAU) || defined(CONFIG_DAC_MCUX_GAU)
POWER_PowerOnGau();
#endif
return 0;
#if CONFIG_PM
nxp_rw6xx_power_init();
#endif
}
void soc_reset_hook(void)
@ -314,5 +314,3 @@ void soc_reset_hook(void)
/* This is provided by the SDK */
SystemInit();
}
SYS_INIT(nxp_rw600_init, PRE_KERNEL_1, 0);

1
soc/nxp/s32/s32k1/Kconfig
View file

@ -19,6 +19,7 @@ config SOC_SERIES_S32K1
select HAS_MCUX_WDOG32
select HAS_MCUX_RTC
select HAS_MCUX_ADC12
select SOC_EARLY_INIT_HOOK
config SOC_S32K116
select CPU_CORTEX_M0PLUS

6
soc/nxp/s32/s32k1/soc.c
View file

@ -48,7 +48,7 @@ void z_arm_watchdog_init(void)
}
#endif /* CONFIG_WDOG_INIT */
static int soc_init(void)
void soc_early_init_hook(void)
{
#if !defined(CONFIG_ARM_MPU)
uint32_t tmp;
@ -71,8 +71,4 @@ static int soc_init(void)
#endif
OsIf_Init(NULL);
return 0;
}
SYS_INIT(soc_init, PRE_KERNEL_1, 0);

1
soc/nxp/s32/s32k3/Kconfig
View file

@ -22,6 +22,7 @@ config SOC_SERIES_S32K3
select HAS_MCUX_LPSPI
select HAS_MCUX_CACHE
select HAS_MCUX_EDMA
select SOC_EARLY_INIT_HOOK
if SOC_SERIES_S32K3

6
soc/nxp/s32/s32k3/soc.c
View file

@ -49,14 +49,10 @@ const struct ivt ivt_header __attribute__((section(".ivt_header"))) = {
};
#endif /* CONFIG_XIP */
static int soc_init(void)
void soc_early_init_hook(void)
{
sys_cache_instr_enable();
sys_cache_data_enable();
OsIf_Init(NULL);
return 0;
}
SYS_INIT(soc_init, PRE_KERNEL_1, 0);

1
soc/nxp/s32/s32ze/Kconfig
View file

@ -18,6 +18,7 @@ config SOC_SERIES_S32ZE
select HAS_MCUX_PIT
select HAS_MCUX_FLEXCAN
select HAS_MCUX_LPI2C
select SOC_EARLY_INIT_HOOK
if SOC_SERIES_S32ZE

6
soc/nxp/s32/s32ze/soc.c
View file

@ -44,11 +44,7 @@ void soc_reset_hook(void)
}
}
static int soc_init(void)
void soc_early_init_hook(void)
{
OsIf_Init(NULL);
return 0;
}
SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);