arch: arm: replace PLATFORM_SPECIFIC_INIT with PLATFORM_RESET_HOOK

Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.

Replace z_arm_platform_init() with platform_reset().

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

arch/arm/core/Kconfig

@@ -166,11 +166,15 @@ config RUNTIME_NMI
 	  needed, enable this option and attach it via z_arm_nmi_set_handler().
 
 config PLATFORM_SPECIFIC_INIT
-	bool "Platform (SOC) specific startup hook"
+	bool "Platform (SOC) specific startup hook [DEPRECATED]"
+	select DEPRECATED
+	select SOC_RESET_HOOK
 	help
 	  The platform specific initialization code (z_arm_platform_init) is
 	  executed at the beginning of the startup code (__start).
 
+	  This option is deprecated, use SOC_RESET_HOOK instead.
+
 config FAULT_DUMP
 	int "Fault dump level"
 	default 2

arch/arm/core/cortex_a_r/reset.S

@@ -30,8 +30,8 @@ GDATA(z_arm_sys_stack)
 GDATA(z_arm_fiq_stack)
 GDATA(z_arm_abort_stack)
 GDATA(z_arm_undef_stack)
-#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
-GTEXT(z_arm_platform_init)
+#if defined(CONFIG_SOC_RESET_HOOK)
+GTEXT(soc_reset_hook)
 #endif
 
 /**
@@ -305,9 +305,9 @@ _primary_core:
     msr CPSR_c, #(MODE_SYS | I_BIT | F_BIT)
     mov sp, r10
 
-#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
+#if defined(CONFIG_SOC_RESET_HOOK)
     /* Execute platform-specific initialisation if applicable */
-    bl z_arm_platform_init
+    bl soc_reset_hook
 #endif
 
 #if defined(CONFIG_WDOG_INIT)

arch/arm/core/cortex_m/reset.S

@@ -24,8 +24,8 @@ GDATA(z_interrupt_stacks)
 #if defined(CONFIG_DEBUG_THREAD_INFO)
 GDATA(z_sys_post_kernel)
 #endif
-#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
-GTEXT(z_arm_platform_init)
+#if defined(CONFIG_SOC_RESET_HOOK)
+GTEXT(soc_reset_hook)
 #endif
 #if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)
 GTEXT(z_arm_init_arch_hw_at_boot)
@@ -93,8 +93,8 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
     bl arch_pm_s2ram_resume
 #endif /* CONFIG_PM_S2RAM */
 
-#if defined(CONFIG_PLATFORM_SPECIFIC_INIT)
-    bl z_arm_platform_init
+#if defined(CONFIG_SOC_RESET_HOOK)
+    bl soc_reset_hook
 #endif
 
 #if defined(CONFIG_INIT_ARCH_HW_AT_BOOT)

drivers/clock_control/clock_control_numaker_scc.c

@@ -136,7 +136,7 @@ static int numaker_scc_init(const struct device *dev)
 #endif
 
 	/*
-	 * z_arm_platform_init() will respect above configurations and
+	 * soc_reset_hook() will respect above configurations and
 	 * actually take charge of system clock control initialization.
 	 */
 

samples/drivers/ipm/ipm_mcux/remote/prj.conf

@@ -1,6 +1,6 @@
 CONFIG_STDOUT_CONSOLE=n
 CONFIG_PRINTK=n
 CONFIG_IPM=y
-CONFIG_PLATFORM_SPECIFIC_INIT=n
+CONFIG_SOC_RESET_HOOK=n
 CONFIG_SECOND_CORE_MCUX=y
 CONFIG_BUILD_OUTPUT_HEX=y

samples/subsys/ipc/openamp/remote/prj.conf

@@ -1,7 +1,7 @@
 CONFIG_STDOUT_CONSOLE=n
 CONFIG_PRINTK=n
 CONFIG_IPM=y
-CONFIG_PLATFORM_SPECIFIC_INIT=n
+CONFIG_SOC_RESET_HOOK=n
 CONFIG_HEAP_MEM_POOL_SIZE=4096
 CONFIG_OPENAMP=y
 CONFIG_SEGGER_RTT_BUFFER_SIZE_UP=4096

samples/subsys/ipc/openamp_rsc_table/boards/colibri_imx7d_mcimx7d_m4.conf

@@ -1,7 +1,7 @@
 CONFIG_IPM=y
 CONFIG_IPM_IMX_MAX_DATA_SIZE_4=y
 CONFIG_OPENAMP_WITH_DCACHE=y
-CONFIG_PLATFORM_SPECIFIC_INIT=n
+CONFIG_SOC_RESET_HOOK=n
 CONFIG_OPENAMP=y
 CONFIG_OPENAMP_RSC_TABLE_NUM_RPMSG_BUFF=32
 CONFIG_OPENAMP_RSC_TABLE=y

samples/subsys/ipc/openamp_rsc_table/boards/stm32mp157c_dk2.conf

@@ -1 +1 @@
-CONFIG_PLATFORM_SPECIFIC_INIT=n
+CONFIG_SOC_RESET_HOOK=n

soc/arm/fvp_aemv8r/Kconfig

@@ -13,5 +13,5 @@ config SOC_FVP_AEMV8R_AARCH32
 	select CPU_HAS_MPU
 	select VFP_DP_D32_FP16_FMAC if !USE_SWITCH
 	select GIC_SINGLE_SECURITY_STATE
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select ARM

soc/arm/fvp_aemv8r/aarch32/soc.c

@@ -8,7 +8,7 @@
 #include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	if (IS_ENABLED(CONFIG_ICACHE)) {
 		if (!(__get_SCTLR() & SCTLR_I_Msk)) {

soc/aspeed/Kconfig

@@ -3,7 +3,7 @@
 # Copyright (c) 2021 ASPEED Technology Inc.
 
 config SOC_FAMILY_ASPEED
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 if SOC_FAMILY_ASPEED
 

soc/aspeed/ast10x0/soc.c

@@ -84,7 +84,7 @@ struct sb_header sbh __attribute((used, section(".sboot"))) = {
 	.img_size = (uint32_t)&__bss_start,
 };
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	uint32_t jtag_pinmux;
 	uint32_t base = DT_REG_ADDR(DT_NODELABEL(syscon));

soc/atmel/sam/sam3x/Kconfig

@@ -11,5 +11,5 @@ config SOC_SERIES_SAM3X
 	select CPU_CORTEX_M3
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select HAS_POWEROFF

soc/atmel/sam/sam3x/soc.c

@@ -97,7 +97,7 @@ static ALWAYS_INLINE void clock_init(void)
 	}
 }
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
 		/*

soc/atmel/sam/sam4e/Kconfig

@@ -11,5 +11,5 @@ config SOC_SERIES_SAM4E
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select HAS_POWEROFF

soc/atmel/sam/sam4e/soc.c

@@ -89,7 +89,7 @@ static ALWAYS_INLINE void clock_init(void)
 	}
 }
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
 		/*

soc/atmel/sam/sam4l/Kconfig

@@ -6,5 +6,5 @@ config SOC_SERIES_SAM4L
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select HAS_POWEROFF

soc/atmel/sam/sam4l/soc.c

@@ -253,7 +253,7 @@ static ALWAYS_INLINE void clock_init(void)
 	PM->MCCTRL = OSC_SRC_PLL0;
 }
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 #if defined(CONFIG_WDT_DISABLE_AT_BOOT)
 	wdt_set_ctrl(WDT->CTRL & ~WDT_CTRL_EN);

soc/atmel/sam/sam4s/Kconfig

@@ -10,5 +10,5 @@ config SOC_SERIES_SAM4S
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select HAS_POWEROFF

soc/atmel/sam/sam4s/soc.c

@@ -95,7 +95,7 @@ static ALWAYS_INLINE void clock_init(void)
 	}
 }
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
 		/*

soc/atmel/sam/same70/Kconfig

@@ -13,7 +13,7 @@ config SOC_SERIES_SAME70
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
 	select INIT_ARCH_HW_AT_BOOT
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select HAS_SWO
 	select XIP
 	select HAS_POWEROFF

soc/atmel/sam/same70/soc.c

@@ -105,7 +105,7 @@ static ALWAYS_INLINE void clock_init(void)
 	}
 }
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
 		/*

soc/atmel/sam/samv71/Kconfig

@@ -13,7 +13,7 @@ config SOC_SERIES_SAMV71
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
 	select INIT_ARCH_HW_AT_BOOT
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select HAS_SWO
 	select XIP
 	select HAS_POWEROFF

soc/atmel/sam/samv71/soc.c

@@ -102,7 +102,7 @@ static ALWAYS_INLINE void clock_init(void)
 	}
 }
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
 		/*

soc/atmel/sam0/common/soc_samc2x.c

@@ -43,7 +43,7 @@ static void gclks_init(void)
 			     | GCLK_GENCTRL_GENEN;
 }
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	flash_waitstates_init();
 	osc48m_init();

soc/atmel/sam0/common/soc_samd2x.c

@@ -286,7 +286,7 @@ static inline void osc8m_disable(void)
 }
 #endif
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	osc8m_init();
 	osc32k_init();

soc/atmel/sam0/common/soc_samd5x.c

@@ -105,7 +105,7 @@ static void gclk_connect(uint8_t gclk, uint8_t src, uint8_t div)
 				| GCLK_GENCTRL_GENEN;
 }
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	uint8_t dfll_div;
 

soc/atmel/sam0/common/soc_saml2x.c

@@ -251,7 +251,7 @@ static inline void pause_for_debug(void)
 static inline void pause_for_debug(void) {}
 #endif
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	pause_for_debug();
 

soc/atmel/sam0/samc20/Kconfig

@@ -9,4 +9,4 @@ config SOC_SERIES_SAMC20
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/atmel/sam0/samc21/Kconfig

@@ -10,4 +10,4 @@ config SOC_SERIES_SAMC21
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
 	select CPU_HAS_ARM_MPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/atmel/sam0/samd20/Kconfig

@@ -9,4 +9,4 @@ config SOC_SERIES_SAMD20
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/atmel/sam0/samd21/Kconfig

@@ -9,4 +9,4 @@ config SOC_SERIES_SAMD21
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/atmel/sam0/samd51/Kconfig

@@ -10,4 +10,4 @@ config SOC_SERIES_SAMD51
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/atmel/sam0/same51/Kconfig

@@ -10,4 +10,4 @@ config SOC_SERIES_SAME51
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/atmel/sam0/same53/Kconfig

@@ -10,4 +10,4 @@ config SOC_SERIES_SAME53
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/atmel/sam0/same54/Kconfig

@@ -10,4 +10,4 @@ config SOC_SERIES_SAME54
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/atmel/sam0/saml21/Kconfig

@@ -9,4 +9,4 @@ config SOC_SERIES_SAML21
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/atmel/sam0/samr21/Kconfig

@@ -9,4 +9,4 @@ config SOC_SERIES_SAMR21
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/atmel/sam0/samr34/Kconfig

@@ -9,4 +9,4 @@ config SOC_SERIES_SAMR34
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/atmel/sam0/samr35/Kconfig

@@ -9,4 +9,4 @@ config SOC_SERIES_SAMR35
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/gd/gd32/gd32a50x/Kconfig

@@ -9,4 +9,4 @@ config SOC_SERIES_GD32A50X
 	select CPU_CORTEX_M33
 	select GD32_HAS_AF_PINMUX
 	select GD32_HAS_IRC_40K
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/gd/gd32/gd32a50x/soc.c

@@ -8,7 +8,7 @@
 #include <soc.h>
 
 /* initial ecc memory */
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	register unsigned r0 __asm("r0") = DT_REG_ADDR(DT_CHOSEN(zephyr_sram));
 	register unsigned r1 __asm("r1") =

soc/infineon/cat3/Kconfig

@@ -5,7 +5,7 @@
 
 config SOC_FAMILY_INFINEON_XMC
 	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 if SOC_FAMILY_INFINEON_XMC
 

soc/infineon/cat3/xmc4xxx/soc.c

@@ -17,7 +17,7 @@
 #define PMU_FLASH_WS		(0x4U)
 #endif
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	uint32_t temp;
 

soc/nordic/Kconfig

@@ -8,7 +8,7 @@
 
 config SOC_FAMILY_NORDIC_NRF
 	select SOC_COMPATIBLE_NRF
-	select PLATFORM_SPECIFIC_INIT if ARM
+	select SOC_RESET_HOOK if ARM
 
 if SOC_FAMILY_NORDIC_NRF
 

soc/nordic/common/CMakeLists.txt

@@ -4,8 +4,8 @@
 add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr)
 
 if(CONFIG_ARM)
-  # Let SystemInit() be called in place of z_arm_platform_init() by default.
-  zephyr_linker_symbol(SYMBOL z_arm_platform_init EXPR "@SystemInit@")
+  # Let SystemInit() be called in place of soc_reset_hook() by default.
+  zephyr_linker_symbol(SYMBOL soc_reset_hook EXPR "@SystemInit@")
 
   # This file is used when the CMake linker script generator is disabled.
   zephyr_linker_sources(SECTIONS arm_platform_init.ld)

soc/nordic/common/arm_platform_init.ld

@@ -4,5 +4,5 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/* Let SystemInit() be called in place of z_arm_platform_init() by default. */
-PROVIDE(z_arm_platform_init = SystemInit);
+/* Let SystemInit() be called in place of soc_reset_hook() by default. */
+PROVIDE(soc_reset_hook = SystemInit);

soc/nuvoton/numaker/Kconfig

@@ -3,7 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_FAMILY_NUMAKER
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 if SOC_FAMILY_NUMAKER
 

soc/nuvoton/numaker/m2l31x/soc.c

@@ -9,7 +9,7 @@
 /* Hardware and starter kit includes. */
 #include <NuMicro.h>
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 

soc/nuvoton/numaker/m46x/soc.c

@@ -9,7 +9,7 @@
 /* Hardware and starter kit includes. */
 #include <NuMicro.h>
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 

soc/nuvoton/numicro/Kconfig

@@ -4,7 +4,7 @@
 # Author: Saravanan Sekar <saravanan@linumiz.com>
 
 config SOC_FAMILY_NUMICRO
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 if SOC_FAMILY_NUMICRO
 

soc/nuvoton/numicro/m48x/soc.c

@@ -8,7 +8,7 @@
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SYS_UnlockReg();
 

soc/nxp/imxrt/imxrt10xx/Kconfig

@@ -6,7 +6,7 @@ config SOC_SERIES_IMXRT10XX
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
 	select ARM
 	select CLOCK_CONTROL

soc/nxp/imxrt/imxrt10xx/soc.c

@@ -353,8 +353,8 @@ static int imxrt_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
-void z_arm_platform_init(void)
+#ifdef CONFIG_SOC_RESET_HOOK
+void soc_reset_hook(void)
 {
 	/* Call CMSIS SystemInit */
 	SystemInit();

soc/nxp/imxrt/imxrt118x/Kconfig

@@ -3,7 +3,7 @@
 
 config SOC_SERIES_IMXRT118X
 	select CPU_CORTEX_M_HAS_DWT
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select INIT_ARCH_HW_AT_BOOT if SOC_MIMXRT1189_CM33
 	select ARM
 	select CLOCK_CONTROL

soc/nxp/imxrt/imxrt118x/soc.c

@@ -413,8 +413,8 @@ static int imxrt_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
-void z_arm_platform_init(void)
+#ifdef CONFIG_SOC_RESET_HOOK
+void soc_reset_hook(void)
 {
 	SystemInit();
 }

soc/nxp/imxrt/imxrt11xx/Kconfig

@@ -4,7 +4,7 @@
 config SOC_SERIES_IMXRT11XX
 	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
 	select CPU_CORTEX_M_HAS_DWT
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select ARM
 	select CLOCK_CONTROL
 	select HAS_MCUX_CACHE

soc/nxp/imxrt/imxrt11xx/soc.c

@@ -729,8 +729,8 @@ static int imxrt_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
-void z_arm_platform_init(void)
+#ifdef CONFIG_SOC_RESET_HOOK
+void soc_reset_hook(void)
 {
 	SystemInit();
 

soc/nxp/imxrt/imxrt5xx/Kconfig

@@ -12,7 +12,7 @@ config SOC_MIMXRT595S_CM33
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select ARMV8_M_DSP
 	select ARM_TRUSTZONE_M
 	select CPU_CORTEX_M_HAS_SYSTICK

soc/nxp/imxrt/imxrt5xx/cm33/soc.c

@@ -187,7 +187,7 @@ static void usb_device_clock_init(void)
 
 #endif
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 #ifndef CONFIG_NXP_IMXRT_BOOT_HEADER
 	/*

soc/nxp/imxrt/imxrt6xx/Kconfig

@@ -6,7 +6,7 @@ config SOC_MIMXRT685S_CM33
 	select CPU_CORTEX_M33
 	select CPU_CORTEX_M_HAS_DWT
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select HAS_PM
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_ARM_MPU

soc/nxp/imxrt/imxrt6xx/cm33/soc.c

@@ -376,9 +376,9 @@ static int nxp_rt600_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 #ifndef CONFIG_NXP_IMXRT_BOOT_HEADER
 	/*

soc/nxp/kinetis/k2x/Kconfig

@@ -13,7 +13,7 @@ config SOC_SERIES_KINETIS_K2X
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_MK22F51212
 	select HAS_MCUX

soc/nxp/kinetis/k2x/soc.c

@@ -129,13 +129,13 @@ static int fsl_frdm_k22f_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(fsl_frdm_k22f_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/k6x/Kconfig

@@ -10,7 +10,7 @@ config SOC_SERIES_KINETIS_K6X
 	select CPU_HAS_NXP_MPU
 	select HAS_MCUX_PIT
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_MK64F12
 	select HAS_MCUX

soc/nxp/kinetis/k6x/soc.c

@@ -166,13 +166,13 @@ static int k6x_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(k6x_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/k8x/Kconfig

@@ -26,7 +26,7 @@ config SOC_SERIES_KINETIS_K8X
 	select HAS_MCUX_PIT
 	select HAS_MCUX_RCM
 	select HAS_MCUX_CACHE
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 if SOC_SERIES_KINETIS_K8X
 

soc/nxp/kinetis/k8x/soc.c

@@ -120,13 +120,13 @@ static int k8x_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(k8x_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/ke1xf/Kconfig

@@ -29,7 +29,7 @@ config SOC_SERIES_KINETIS_KE1XF
 	select HAS_MCUX_EDMA
 	select HAS_MCUX_PWT
 	select HAS_MCUX_RCM
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select HAS_PM
 
 config SOC_MKE16F16

soc/nxp/kinetis/ke1xf/soc.c

@@ -268,7 +268,7 @@ static int ke1xf_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
 #ifdef CONFIG_WDOG_INIT
 
@@ -307,12 +307,12 @@ void z_arm_watchdog_init(void)
 
 #endif /* CONFIG_WDOG_INIT */
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	/* SystemInit is provided by the NXP SDK */
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(ke1xf_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/ke1xz/Kconfig

@@ -11,5 +11,5 @@ config SOC_SERIES_KE1XZ
 	select CPU_CORTEX_M_HAS_VTOR
 	select CLOCK_CONTROL
 	select HAS_MCUX
-	select PLATFORM_SPECIFIC_INIT
 	select HAS_PM
+	select SOC_RESET_HOOK

soc/nxp/kinetis/ke1xz/soc.c

@@ -153,14 +153,14 @@ static int ke1xz_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	/* SystemInit is provided by the NXP SDK */
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(ke1xz_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/kl2x/Kconfig

@@ -9,7 +9,7 @@ config SOC_SERIES_KINETIS_KL2X
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_MKL25Z4
 	select CPU_CORTEX_M0PLUS

soc/nxp/kinetis/kl2x/soc.c

@@ -87,13 +87,13 @@ static int kl2x_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(kl2x_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/kv5x/Kconfig

@@ -21,4 +21,4 @@ config SOC_SERIES_KINETIS_KV5X
 	select HAS_OSC
 	select HAS_MCG
 	select HAS_MCUX_RCM
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/nxp/kinetis/kv5x/soc.c

@@ -97,13 +97,13 @@ static int kv5x_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(kv5x_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/kwx/Kconfig

@@ -8,7 +8,7 @@ config SOC_SERIES_KINETIS_KWX
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_MKW22D5
 	select CPU_CORTEX_M4

soc/nxp/kinetis/kwx/soc_kw2xd.c

@@ -158,13 +158,13 @@ static int kw2xd_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(kw2xd_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/kwx/soc_kw4xz.c

@@ -87,13 +87,13 @@ static int kwx_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(kwx_init, PRE_KERNEL_1, 0);

soc/nxp/lpc/lpc51u68/Kconfig

@@ -15,7 +15,7 @@ config SOC_SERIES_LPC51U68
 	select HAS_MCUX_SCTIMER
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_LPC51U68
 	select CLOCK_CONTROL

soc/nxp/lpc/lpc51u68/soc.c

@@ -46,13 +46,13 @@ int soc_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(soc_init, PRE_KERNEL_1, 0);

soc/nxp/lpc/lpc54xxx/CMakeLists.txt

@@ -6,7 +6,7 @@
 zephyr_library()
 
 zephyr_library_sources(soc.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT gcc/startup_LPC54114_cm4.S)
+zephyr_library_sources_ifdef(CONFIG_SOC_RESET_HOOK gcc/startup_LPC54114_cm4.S)
 
 zephyr_library_include_directories(
   ${ZEPHYR_BASE}/kernel/include

soc/nxp/lpc/lpc54xxx/Kconfig

@@ -9,14 +9,14 @@ config SOC_SERIES_LPC54XXX
 	select HAS_MCUX_FLEXCOMM
 	select HAS_MCUX_SYSCON
 	select CPU_CORTEX_M_HAS_SYSTICK
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_LPC54114_M4
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select CLOCK_CONTROL
 	select HAS_MCUX_IAP_LEGACY
 

soc/nxp/lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S

@@ -11,7 +11,7 @@
 #include <zephyr/linker/sections.h>
 #include <zephyr/arch/cpu.h>
 
-#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) && defined(CONFIG_SOC_LPC54114_M4)
+#if defined(CONFIG_SOC_RESET_HOOK) && defined(CONFIG_SOC_LPC54114_M4)
 
     .syntax unified
     .arch armv7-m
@@ -26,8 +26,8 @@ rel_vals:
     .short  0x0FFF
     .short  0x0C24
 
-GTEXT(z_arm_platform_init)
-SECTION_FUNC(TEXT,z_arm_platform_init)
+GTEXT(soc_reset_hook)
+SECTION_FUNC(TEXT,soc_reset_hook)
 
 /* Both the M0+ and M4 core come via this shared startup code,
  * but the M0+ and M4 core have different vector tables.

soc/nxp/lpc/lpc54xxx/soc.c

@@ -116,17 +116,17 @@ static int nxp_lpc54114_init(void)
 
 SYS_INIT(nxp_lpc54114_init, PRE_KERNEL_1, 0);
 
-#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) && defined(CONFIG_SOC_LPC54114_M0)
+#if defined(CONFIG_SOC_RESET_HOOK) && defined(CONFIG_SOC_LPC54114_M0)
 
 /* M4 core has a custom platform initialization routine in assembly,
  * but M0 core does not. install one here to call SystemInit.
  */
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 
 #if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC54114_M4)

soc/nxp/lpc/lpc55xxx/Kconfig

@@ -8,7 +8,7 @@ config SOC_SERIES_LPC55XXX
 	select HAS_MCUX_WWDT
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_DWT
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_LPC55S06
 	select CPU_CORTEX_M33

soc/nxp/lpc/lpc55xxx/soc.c

@@ -369,9 +369,9 @@ static int nxp_lpc55xxx_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 
@@ -385,7 +385,7 @@ void z_arm_platform_init(void)
 #endif
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(nxp_lpc55xxx_init, PRE_KERNEL_1, 0);
 

soc/nxp/mcx/mcxn/Kconfig

@@ -9,7 +9,7 @@ config SOC_SERIES_MCXN
 	select HAS_MCUX_FLEXCOMM
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_DWT
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_MCXN947_CPU0
 	select CPU_CORTEX_M33

soc/nxp/mcx/mcxn/soc.c

@@ -17,9 +17,9 @@
 #include <zephyr/init.h>
 #include <soc.h>
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }

soc/nxp/rw/Kconfig

@@ -6,7 +6,7 @@ config SOC_SERIES_RW6XX
 	select CPU_CORTEX_M33
 	select CPU_CORTEX_M_HAS_DWT
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU

soc/nxp/rw/soc.c

@@ -309,7 +309,7 @@ static int nxp_rw600_init(void)
 	return 0;
 }
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	/* This is provided by the SDK */
 	SystemInit();

soc/nxp/s32/s32k3/CMakeLists.txt

@@ -10,6 +10,6 @@ zephyr_library_sources_ifdef(CONFIG_DT_HAS_NXP_S32K3_PMC_ENABLED pmc.c)
 
 zephyr_library_sources_ifdef(CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS mpu_regions.c)
 zephyr_linker_sources(SECTIONS sections.ld)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT s32k3xx_startup.S)
+zephyr_library_sources_ifdef(CONFIG_SOC_RESET_HOOK s32k3xx_startup.S)
 
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/nxp/s32/s32k3/Kconfig

@@ -12,7 +12,7 @@ config SOC_SERIES_S32K3
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
 	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
-	select PLATFORM_SPECIFIC_INIT if XIP
+	select SOC_RESET_HOOK if XIP
 	select USE_DT_CODE_PARTITION if XIP
 	select CLOCK_CONTROL
 	select HAS_MCUX

soc/nxp/s32/s32k3/s32k3xx_startup.S

@@ -14,9 +14,9 @@
 
 _ASM_FILE_PROLOGUE
 
-GTEXT(z_arm_platform_init)
+GTEXT(soc_reset_hook)
 
-SECTION_FUNC(TEXT, z_arm_platform_init)
+SECTION_FUNC(TEXT, soc_reset_hook)
 
 	/*
 	 * On destructive reset, SRAM and TCM memories must be initialized to a known value using a

soc/nxp/s32/s32ze/Kconfig

@@ -11,7 +11,7 @@ config SOC_SERIES_S32ZE
 	select CPU_HAS_ARM_MPU
 	select GIC_SINGLE_SECURITY_STATE
 	select VFP_DP_D16
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select CLOCK_CONTROL
 	select HAS_NXP_S32_HAL
 	select HAS_MCUX

soc/nxp/s32/s32ze/soc.c

@@ -12,7 +12,7 @@
 
 #include <OsIf.h>
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	/* enable peripheral port access at EL1 and EL0 */
 	__asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");

soc/renesas/rcar/rcar_gen3/Kconfig

@@ -7,7 +7,7 @@ config SOC_SERIES_RCAR_GEN3
 config SOC_R8A77951_R7
 	select ARM
 	select CPU_CORTEX_R7
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select CPU_HAS_DCLS
 
 config SOC_R8A77951_A57

soc/renesas/rcar/rcar_gen3/r7/soc.c

@@ -9,7 +9,7 @@
 #include <zephyr/device.h>
 #include <zephyr/sys/barrier.h>
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	L1C_DisableCaches();
 	L1C_DisableBTAC();

soc/renesas/smartbond/da1469x/Kconfig

@@ -12,6 +12,6 @@ config SOC_SERIES_DA1469X
 	select HAS_PM
 	select CLOCK_CONTROL
 	select CLOCK_CONTROL_SMARTBOND
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select PM_DEVICE if PM
 	imply TIMER_READS_ITS_FREQUENCY_AT_RUNTIME

soc/renesas/smartbond/da1469x/soc.c

@@ -109,7 +109,7 @@ static void z_renesas_configure_cache(void)
 }
 #endif /* CONFIG_HAS_FLASH_LOAD_OFFSET */
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 #if defined(CONFIG_PM)
 	uint32_t *ivt;