arch: arm: replace PLATFORM_SPECIFIC_INIT with PLATFORM_RESET_HOOK

Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.

Replace z_arm_platform_init() with platform_reset().

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

soc/nxp/imxrt/imxrt10xx/Kconfig

@@ -6,7 +6,7 @@ config SOC_SERIES_IMXRT10XX
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
 	select ARM
 	select CLOCK_CONTROL

soc/nxp/imxrt/imxrt10xx/soc.c

@@ -353,8 +353,8 @@ static int imxrt_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
-void z_arm_platform_init(void)
+#ifdef CONFIG_SOC_RESET_HOOK
+void soc_reset_hook(void)
 {
 	/* Call CMSIS SystemInit */
 	SystemInit();

soc/nxp/imxrt/imxrt118x/Kconfig

@@ -3,7 +3,7 @@
 
 config SOC_SERIES_IMXRT118X
 	select CPU_CORTEX_M_HAS_DWT
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select INIT_ARCH_HW_AT_BOOT if SOC_MIMXRT1189_CM33
 	select ARM
 	select CLOCK_CONTROL

soc/nxp/imxrt/imxrt118x/soc.c

@@ -413,8 +413,8 @@ static int imxrt_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
-void z_arm_platform_init(void)
+#ifdef CONFIG_SOC_RESET_HOOK
+void soc_reset_hook(void)
 {
 	SystemInit();
 }

soc/nxp/imxrt/imxrt11xx/Kconfig

@@ -4,7 +4,7 @@
 config SOC_SERIES_IMXRT11XX
 	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
 	select CPU_CORTEX_M_HAS_DWT
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select ARM
 	select CLOCK_CONTROL
 	select HAS_MCUX_CACHE

soc/nxp/imxrt/imxrt11xx/soc.c

@@ -729,8 +729,8 @@ static int imxrt_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
-void z_arm_platform_init(void)
+#ifdef CONFIG_SOC_RESET_HOOK
+void soc_reset_hook(void)
 {
 	SystemInit();
 

soc/nxp/imxrt/imxrt5xx/Kconfig

@@ -12,7 +12,7 @@ config SOC_MIMXRT595S_CM33
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select ARMV8_M_DSP
 	select ARM_TRUSTZONE_M
 	select CPU_CORTEX_M_HAS_SYSTICK

soc/nxp/imxrt/imxrt5xx/cm33/soc.c

@@ -187,7 +187,7 @@ static void usb_device_clock_init(void)
 
 #endif
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 #ifndef CONFIG_NXP_IMXRT_BOOT_HEADER
 	/*

soc/nxp/imxrt/imxrt6xx/Kconfig

@@ -6,7 +6,7 @@ config SOC_MIMXRT685S_CM33
 	select CPU_CORTEX_M33
 	select CPU_CORTEX_M_HAS_DWT
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select HAS_PM
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_ARM_MPU

soc/nxp/imxrt/imxrt6xx/cm33/soc.c

@@ -376,9 +376,9 @@ static int nxp_rt600_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 #ifndef CONFIG_NXP_IMXRT_BOOT_HEADER
 	/*

soc/nxp/kinetis/k2x/Kconfig

@@ -13,7 +13,7 @@ config SOC_SERIES_KINETIS_K2X
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_MK22F51212
 	select HAS_MCUX

soc/nxp/kinetis/k2x/soc.c

@@ -129,13 +129,13 @@ static int fsl_frdm_k22f_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(fsl_frdm_k22f_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/k6x/Kconfig

@@ -10,7 +10,7 @@ config SOC_SERIES_KINETIS_K6X
 	select CPU_HAS_NXP_MPU
 	select HAS_MCUX_PIT
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_MK64F12
 	select HAS_MCUX

soc/nxp/kinetis/k6x/soc.c

@@ -166,13 +166,13 @@ static int k6x_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(k6x_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/k8x/Kconfig

@@ -26,7 +26,7 @@ config SOC_SERIES_KINETIS_K8X
 	select HAS_MCUX_PIT
 	select HAS_MCUX_RCM
 	select HAS_MCUX_CACHE
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 if SOC_SERIES_KINETIS_K8X
 

soc/nxp/kinetis/k8x/soc.c

@@ -120,13 +120,13 @@ static int k8x_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(k8x_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/ke1xf/Kconfig

@@ -29,7 +29,7 @@ config SOC_SERIES_KINETIS_KE1XF
 	select HAS_MCUX_EDMA
 	select HAS_MCUX_PWT
 	select HAS_MCUX_RCM
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select HAS_PM
 
 config SOC_MKE16F16

soc/nxp/kinetis/ke1xf/soc.c

@@ -268,7 +268,7 @@ static int ke1xf_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
 #ifdef CONFIG_WDOG_INIT
 
@@ -307,12 +307,12 @@ void z_arm_watchdog_init(void)
 
 #endif /* CONFIG_WDOG_INIT */
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	/* SystemInit is provided by the NXP SDK */
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(ke1xf_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/ke1xz/Kconfig

@@ -11,5 +11,5 @@ config SOC_SERIES_KE1XZ
 	select CPU_CORTEX_M_HAS_VTOR
 	select CLOCK_CONTROL
 	select HAS_MCUX
-	select PLATFORM_SPECIFIC_INIT
 	select HAS_PM
+	select SOC_RESET_HOOK

soc/nxp/kinetis/ke1xz/soc.c

@@ -153,14 +153,14 @@ static int ke1xz_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	/* SystemInit is provided by the NXP SDK */
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(ke1xz_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/kl2x/Kconfig

@@ -9,7 +9,7 @@ config SOC_SERIES_KINETIS_KL2X
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_MKL25Z4
 	select CPU_CORTEX_M0PLUS

soc/nxp/kinetis/kl2x/soc.c

@@ -87,13 +87,13 @@ static int kl2x_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(kl2x_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/kv5x/Kconfig

@@ -21,4 +21,4 @@ config SOC_SERIES_KINETIS_KV5X
 	select HAS_OSC
 	select HAS_MCG
 	select HAS_MCUX_RCM
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK

soc/nxp/kinetis/kv5x/soc.c

@@ -97,13 +97,13 @@ static int kv5x_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(kv5x_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/kwx/Kconfig

@@ -8,7 +8,7 @@ config SOC_SERIES_KINETIS_KWX
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_MKW22D5
 	select CPU_CORTEX_M4

soc/nxp/kinetis/kwx/soc_kw2xd.c

@@ -158,13 +158,13 @@ static int kw2xd_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(kw2xd_init, PRE_KERNEL_1, 0);

soc/nxp/kinetis/kwx/soc_kw4xz.c

@@ -87,13 +87,13 @@ static int kwx_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(kwx_init, PRE_KERNEL_1, 0);

soc/nxp/lpc/lpc51u68/Kconfig

@@ -15,7 +15,7 @@ config SOC_SERIES_LPC51U68
 	select HAS_MCUX_SCTIMER
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_VTOR
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_LPC51U68
 	select CLOCK_CONTROL

soc/nxp/lpc/lpc51u68/soc.c

@@ -46,13 +46,13 @@ int soc_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(soc_init, PRE_KERNEL_1, 0);

soc/nxp/lpc/lpc54xxx/CMakeLists.txt

@@ -6,7 +6,7 @@
 zephyr_library()
 
 zephyr_library_sources(soc.c)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT gcc/startup_LPC54114_cm4.S)
+zephyr_library_sources_ifdef(CONFIG_SOC_RESET_HOOK gcc/startup_LPC54114_cm4.S)
 
 zephyr_library_include_directories(
   ${ZEPHYR_BASE}/kernel/include

soc/nxp/lpc/lpc54xxx/Kconfig

@@ -9,14 +9,14 @@ config SOC_SERIES_LPC54XXX
 	select HAS_MCUX_FLEXCOMM
 	select HAS_MCUX_SYSCON
 	select CPU_CORTEX_M_HAS_SYSTICK
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_LPC54114_M4
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select CLOCK_CONTROL
 	select HAS_MCUX_IAP_LEGACY
 

soc/nxp/lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S

@@ -11,7 +11,7 @@
 #include <zephyr/linker/sections.h>
 #include <zephyr/arch/cpu.h>
 
-#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) && defined(CONFIG_SOC_LPC54114_M4)
+#if defined(CONFIG_SOC_RESET_HOOK) && defined(CONFIG_SOC_LPC54114_M4)
 
     .syntax unified
     .arch armv7-m
@@ -26,8 +26,8 @@ rel_vals:
     .short  0x0FFF
     .short  0x0C24
 
-GTEXT(z_arm_platform_init)
-SECTION_FUNC(TEXT,z_arm_platform_init)
+GTEXT(soc_reset_hook)
+SECTION_FUNC(TEXT,soc_reset_hook)
 
 /* Both the M0+ and M4 core come via this shared startup code,
  * but the M0+ and M4 core have different vector tables.

soc/nxp/lpc/lpc54xxx/soc.c

@@ -116,17 +116,17 @@ static int nxp_lpc54114_init(void)
 
 SYS_INIT(nxp_lpc54114_init, PRE_KERNEL_1, 0);
 
-#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) && defined(CONFIG_SOC_LPC54114_M0)
+#if defined(CONFIG_SOC_RESET_HOOK) && defined(CONFIG_SOC_LPC54114_M0)
 
 /* M4 core has a custom platform initialization routine in assembly,
  * but M0 core does not. install one here to call SystemInit.
  */
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 
 #if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC54114_M4)

soc/nxp/lpc/lpc55xxx/Kconfig

@@ -8,7 +8,7 @@ config SOC_SERIES_LPC55XXX
 	select HAS_MCUX_WWDT
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_DWT
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_LPC55S06
 	select CPU_CORTEX_M33

soc/nxp/lpc/lpc55xxx/soc.c

@@ -369,9 +369,9 @@ static int nxp_lpc55xxx_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 
@@ -385,7 +385,7 @@ void z_arm_platform_init(void)
 #endif
 }
 
-#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+#endif /* CONFIG_SOC_RESET_HOOK */
 
 SYS_INIT(nxp_lpc55xxx_init, PRE_KERNEL_1, 0);
 

soc/nxp/mcx/mcxn/Kconfig

@@ -9,7 +9,7 @@ config SOC_SERIES_MCXN
 	select HAS_MCUX_FLEXCOMM
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_DWT
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 
 config SOC_MCXN947_CPU0
 	select CPU_CORTEX_M33

soc/nxp/mcx/mcxn/soc.c

@@ -17,9 +17,9 @@
 #include <zephyr/init.h>
 #include <soc.h>
 
-#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+#ifdef CONFIG_SOC_RESET_HOOK
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	SystemInit();
 }

soc/nxp/rw/Kconfig

@@ -6,7 +6,7 @@ config SOC_SERIES_RW6XX
 	select CPU_CORTEX_M33
 	select CPU_CORTEX_M_HAS_DWT
 	select CLOCK_CONTROL
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU

soc/nxp/rw/soc.c

@@ -309,7 +309,7 @@ static int nxp_rw600_init(void)
 	return 0;
 }
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	/* This is provided by the SDK */
 	SystemInit();

soc/nxp/s32/s32k3/CMakeLists.txt

@@ -10,6 +10,6 @@ zephyr_library_sources_ifdef(CONFIG_DT_HAS_NXP_S32K3_PMC_ENABLED pmc.c)
 
 zephyr_library_sources_ifdef(CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS mpu_regions.c)
 zephyr_linker_sources(SECTIONS sections.ld)
-zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT s32k3xx_startup.S)
+zephyr_library_sources_ifdef(CONFIG_SOC_RESET_HOOK s32k3xx_startup.S)
 
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/nxp/s32/s32k3/Kconfig

@@ -12,7 +12,7 @@ config SOC_SERIES_S32K3
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
 	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
-	select PLATFORM_SPECIFIC_INIT if XIP
+	select SOC_RESET_HOOK if XIP
 	select USE_DT_CODE_PARTITION if XIP
 	select CLOCK_CONTROL
 	select HAS_MCUX

soc/nxp/s32/s32k3/s32k3xx_startup.S

@@ -14,9 +14,9 @@
 
 _ASM_FILE_PROLOGUE
 
-GTEXT(z_arm_platform_init)
+GTEXT(soc_reset_hook)
 
-SECTION_FUNC(TEXT, z_arm_platform_init)
+SECTION_FUNC(TEXT, soc_reset_hook)
 
 	/*
 	 * On destructive reset, SRAM and TCM memories must be initialized to a known value using a

soc/nxp/s32/s32ze/Kconfig

@@ -11,7 +11,7 @@ config SOC_SERIES_S32ZE
 	select CPU_HAS_ARM_MPU
 	select GIC_SINGLE_SECURITY_STATE
 	select VFP_DP_D16
-	select PLATFORM_SPECIFIC_INIT
+	select SOC_RESET_HOOK
 	select CLOCK_CONTROL
 	select HAS_NXP_S32_HAL
 	select HAS_MCUX

soc/nxp/s32/s32ze/soc.c

@@ -12,7 +12,7 @@
 
 #include <OsIf.h>
 
-void z_arm_platform_init(void)
+void soc_reset_hook(void)
 {
 	/* enable peripheral port access at EL1 and EL0 */
 	__asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");