arch: arm: replace PLATFORM_SPECIFIC_INIT with PLATFORM_RESET_HOOK
Use generic hook infrastrucutre instead of custom Kconfig and hooks for ARM. Replace z_arm_platform_init() with platform_reset(). Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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e260d03686
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f519dd1411
105 changed files with 150 additions and 146 deletions
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@ -11,5 +11,5 @@ config SOC_SERIES_SAM3X
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select CPU_CORTEX_M3
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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select HAS_POWEROFF
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@ -97,7 +97,7 @@ static ALWAYS_INLINE void clock_init(void)
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}
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}
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void z_arm_platform_init(void)
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void soc_reset_hook(void)
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{
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
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/*
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@ -11,5 +11,5 @@ config SOC_SERIES_SAM4E
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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select HAS_POWEROFF
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@ -89,7 +89,7 @@ static ALWAYS_INLINE void clock_init(void)
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}
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}
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void z_arm_platform_init(void)
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void soc_reset_hook(void)
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{
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
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/*
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@ -6,5 +6,5 @@ config SOC_SERIES_SAM4L
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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select HAS_POWEROFF
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@ -253,7 +253,7 @@ static ALWAYS_INLINE void clock_init(void)
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PM->MCCTRL = OSC_SRC_PLL0;
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}
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void z_arm_platform_init(void)
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void soc_reset_hook(void)
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{
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#if defined(CONFIG_WDT_DISABLE_AT_BOOT)
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wdt_set_ctrl(WDT->CTRL & ~WDT_CTRL_EN);
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@ -10,5 +10,5 @@ config SOC_SERIES_SAM4S
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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select HAS_POWEROFF
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@ -95,7 +95,7 @@ static ALWAYS_INLINE void clock_init(void)
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}
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}
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void z_arm_platform_init(void)
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void soc_reset_hook(void)
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{
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
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/*
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@ -13,7 +13,7 @@ config SOC_SERIES_SAME70
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select CPU_HAS_ICACHE
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select CPU_HAS_DCACHE
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select INIT_ARCH_HW_AT_BOOT
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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select HAS_SWO
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select XIP
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select HAS_POWEROFF
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@ -105,7 +105,7 @@ static ALWAYS_INLINE void clock_init(void)
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}
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}
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void z_arm_platform_init(void)
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void soc_reset_hook(void)
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{
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
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/*
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@ -13,7 +13,7 @@ config SOC_SERIES_SAMV71
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select CPU_HAS_ICACHE
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select CPU_HAS_DCACHE
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select INIT_ARCH_HW_AT_BOOT
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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select HAS_SWO
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select XIP
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select HAS_POWEROFF
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@ -102,7 +102,7 @@ static ALWAYS_INLINE void clock_init(void)
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}
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}
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void z_arm_platform_init(void)
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void soc_reset_hook(void)
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{
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
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/*
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@ -43,7 +43,7 @@ static void gclks_init(void)
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| GCLK_GENCTRL_GENEN;
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}
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void z_arm_platform_init(void)
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void soc_reset_hook(void)
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{
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flash_waitstates_init();
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osc48m_init();
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@ -286,7 +286,7 @@ static inline void osc8m_disable(void)
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}
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#endif
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void z_arm_platform_init(void)
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void soc_reset_hook(void)
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{
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osc8m_init();
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osc32k_init();
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@ -105,7 +105,7 @@ static void gclk_connect(uint8_t gclk, uint8_t src, uint8_t div)
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| GCLK_GENCTRL_GENEN;
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}
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void z_arm_platform_init(void)
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void soc_reset_hook(void)
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{
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uint8_t dfll_div;
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@ -251,7 +251,7 @@ static inline void pause_for_debug(void)
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static inline void pause_for_debug(void) {}
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#endif
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void z_arm_platform_init(void)
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void soc_reset_hook(void)
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{
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pause_for_debug();
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@ -9,4 +9,4 @@ config SOC_SERIES_SAMC20
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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@ -10,4 +10,4 @@ config SOC_SERIES_SAMC21
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select CPU_HAS_ARM_MPU
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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@ -9,4 +9,4 @@ config SOC_SERIES_SAMD20
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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@ -9,4 +9,4 @@ config SOC_SERIES_SAMD21
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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@ -10,4 +10,4 @@ config SOC_SERIES_SAMD51
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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@ -10,4 +10,4 @@ config SOC_SERIES_SAME51
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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@ -10,4 +10,4 @@ config SOC_SERIES_SAME53
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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@ -10,4 +10,4 @@ config SOC_SERIES_SAME54
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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@ -9,4 +9,4 @@ config SOC_SERIES_SAML21
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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@ -9,4 +9,4 @@ config SOC_SERIES_SAMR21
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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@ -9,4 +9,4 @@ config SOC_SERIES_SAMR34
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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@ -9,4 +9,4 @@ config SOC_SERIES_SAMR35
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select PLATFORM_SPECIFIC_INIT
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select SOC_RESET_HOOK
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