arch: arm: replace PLATFORM_SPECIFIC_INIT with PLATFORM_RESET_HOOK

Use generic hook infrastrucutre instead of custom Kconfig and hooks for
ARM.

Replace z_arm_platform_init() with platform_reset().

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2024-08-06 09:17:48 -04:00 committed by Carles Cufí
commit f519dd1411
105 changed files with 150 additions and 146 deletions

View file

@ -11,5 +11,5 @@ config SOC_SERIES_SAM3X
select CPU_CORTEX_M3
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK
select HAS_POWEROFF

View file

@ -97,7 +97,7 @@ static ALWAYS_INLINE void clock_init(void)
}
}
void z_arm_platform_init(void)
void soc_reset_hook(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
/*

View file

@ -11,5 +11,5 @@ config SOC_SERIES_SAM4E
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK
select HAS_POWEROFF

View file

@ -89,7 +89,7 @@ static ALWAYS_INLINE void clock_init(void)
}
}
void z_arm_platform_init(void)
void soc_reset_hook(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
/*

View file

@ -6,5 +6,5 @@ config SOC_SERIES_SAM4L
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK
select HAS_POWEROFF

View file

@ -253,7 +253,7 @@ static ALWAYS_INLINE void clock_init(void)
PM->MCCTRL = OSC_SRC_PLL0;
}
void z_arm_platform_init(void)
void soc_reset_hook(void)
{
#if defined(CONFIG_WDT_DISABLE_AT_BOOT)
wdt_set_ctrl(WDT->CTRL & ~WDT_CTRL_EN);

View file

@ -10,5 +10,5 @@ config SOC_SERIES_SAM4S
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK
select HAS_POWEROFF

View file

@ -95,7 +95,7 @@ static ALWAYS_INLINE void clock_init(void)
}
}
void z_arm_platform_init(void)
void soc_reset_hook(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
/*

View file

@ -13,7 +13,7 @@ config SOC_SERIES_SAME70
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select INIT_ARCH_HW_AT_BOOT
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK
select HAS_SWO
select XIP
select HAS_POWEROFF

View file

@ -105,7 +105,7 @@ static ALWAYS_INLINE void clock_init(void)
}
}
void z_arm_platform_init(void)
void soc_reset_hook(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
/*

View file

@ -13,7 +13,7 @@ config SOC_SERIES_SAMV71
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select INIT_ARCH_HW_AT_BOOT
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK
select HAS_SWO
select XIP
select HAS_POWEROFF

View file

@ -102,7 +102,7 @@ static ALWAYS_INLINE void clock_init(void)
}
}
void z_arm_platform_init(void)
void soc_reset_hook(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
/*

View file

@ -43,7 +43,7 @@ static void gclks_init(void)
| GCLK_GENCTRL_GENEN;
}
void z_arm_platform_init(void)
void soc_reset_hook(void)
{
flash_waitstates_init();
osc48m_init();

View file

@ -286,7 +286,7 @@ static inline void osc8m_disable(void)
}
#endif
void z_arm_platform_init(void)
void soc_reset_hook(void)
{
osc8m_init();
osc32k_init();

View file

@ -105,7 +105,7 @@ static void gclk_connect(uint8_t gclk, uint8_t src, uint8_t div)
| GCLK_GENCTRL_GENEN;
}
void z_arm_platform_init(void)
void soc_reset_hook(void)
{
uint8_t dfll_div;

View file

@ -251,7 +251,7 @@ static inline void pause_for_debug(void)
static inline void pause_for_debug(void) {}
#endif
void z_arm_platform_init(void)
void soc_reset_hook(void)
{
pause_for_debug();

View file

@ -9,4 +9,4 @@ config SOC_SERIES_SAMC20
select CPU_CORTEX_M0PLUS
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK

View file

@ -10,4 +10,4 @@ config SOC_SERIES_SAMC21
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select CPU_HAS_ARM_MPU
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK

View file

@ -9,4 +9,4 @@ config SOC_SERIES_SAMD20
select CPU_CORTEX_M0PLUS
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK

View file

@ -9,4 +9,4 @@ config SOC_SERIES_SAMD21
select CPU_CORTEX_M0PLUS
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK

View file

@ -10,4 +10,4 @@ config SOC_SERIES_SAMD51
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK

View file

@ -10,4 +10,4 @@ config SOC_SERIES_SAME51
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK

View file

@ -10,4 +10,4 @@ config SOC_SERIES_SAME53
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK

View file

@ -10,4 +10,4 @@ config SOC_SERIES_SAME54
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK

View file

@ -9,4 +9,4 @@ config SOC_SERIES_SAML21
select CPU_CORTEX_M0PLUS
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK

View file

@ -9,4 +9,4 @@ config SOC_SERIES_SAMR21
select CPU_CORTEX_M0PLUS
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK

View file

@ -9,4 +9,4 @@ config SOC_SERIES_SAMR34
select CPU_CORTEX_M0PLUS
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK

View file

@ -9,4 +9,4 @@ config SOC_SERIES_SAMR35
select CPU_CORTEX_M0PLUS
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select PLATFORM_SPECIFIC_INIT
select SOC_RESET_HOOK