From f51674ac24e3a819aec86a0643bc96aadabc8ed4 Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Wed, 1 Jun 2022 15:48:40 +0200 Subject: [PATCH] arch: x86: core: early_serial: obtain NS16550 uart base address from DT The NS16550 UART base address was hardcoded in headers. This bypasses the console choice defined in Devicetree. Hardcoded hardware choices must be avoided now that DT is in place. Signed-off-by: Gerard Marull-Paretas --- arch/x86/core/early_serial.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/core/early_serial.c b/arch/x86/core/early_serial.c index 2d6a3e340e4..027c88c1a61 100644 --- a/arch/x86/core/early_serial.c +++ b/arch/x86/core/early_serial.c @@ -11,10 +11,10 @@ #include -#ifdef UART_NS16550_ACCESS_IOPORT +#ifdef CONFIG_UART_NS16550_ACCESS_IOPORT /* Legacy I/O Port Access to a NS16550 UART */ -#define IN(reg) sys_in8(reg + UART_NS16550_ACCESS_IOPORT) -#define OUT(reg, val) sys_out8(val, reg + UART_NS16550_ACCESS_IOPORT) +#define IN(reg) sys_in8(reg + DT_REG_ADDR(DT_CHOSEN(zephyr_console))) +#define OUT(reg, val) sys_out8(val, reg + DT_REG_ADDR(DT_CHOSEN(zephyr_console))) #elif defined(X86_SOC_EARLY_SERIAL_PCIDEV) /* "Modern" mapping of a UART into a PCI MMIO device. The registers * are still bytes, but spaced at a 32 bit stride instead of packed @@ -86,7 +86,7 @@ int arch_printk_char_out(int c) void z_x86_early_serial_init(void) { -#if defined(DEVICE_MMIO_IS_IN_RAM) && !defined(UART_NS16550_ACCESS_IOPORT) +#if defined(DEVICE_MMIO_IS_IN_RAM) && !defined(CONFIG_UART_NS16550_ACCESS_IOPORT) #ifdef X86_SOC_EARLY_SERIAL_PCIDEV struct pcie_mbar mbar; pcie_get_mbar(X86_SOC_EARLY_SERIAL_PCIDEV, 0, &mbar);