diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
index bcff4490a8b..368d1e86fba 100644
--- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
@@ -26,8 +26,6 @@
 #define RAM_SIZE \
 	(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
 
-#define LPSRAM_MASK(x)		0x00000003
-
 /* Location for the intList section which is later used to construct the
  * Interrupt Descriptor Table (IDT). This is a bogus address as this
  * section will be stripped off in the final image.
@@ -137,9 +135,6 @@
 
 #define SRAM_REG_FW_END		0x14
 
-/* Host page size */
-#define HOST_PAGE_SIZE		4096
-
 /* low power ram where DMA buffers are typically placed */
 #define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
 #define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
index cd4d45cd67d..632ea09f909 100644
--- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
@@ -21,8 +21,6 @@
 #define RAM_SIZE \
 	(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
 
-#define LPSRAM_MASK(x)		0x00000003
-
 /* Location for the intList section which is later used to construct the
  * Interrupt Descriptor Table (IDT). This is a bogus address as this
  * section will be stripped off in the final image.
@@ -135,11 +133,6 @@
 	(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + \
 	 (PLATFORM_CORE_COUNT - 1) * 0x4)
 
-/* Host page size */
-#define HOST_PAGE_SIZE		4096
-
-#define SRAM_BANK_SIZE                  (64 * 1024)
-
 /* low power ram where DMA buffers are typically placed */
 #define LP_SRAM_BASE			(DT_REG_ADDR(DT_NODELABEL(sram1)))
 #define LP_SRAM_SIZE			(DT_REG_SIZE(DT_NODELABEL(sram1)))
diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
index 7074ee04f45..ce23c5d5265 100644
--- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
@@ -21,8 +21,6 @@
 #define RAM_SIZE \
 	(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
 
-#define LPSRAM_MASK(x)		0x00000003
-
 /* Location for the intList section which is later used to construct the
  * Interrupt Descriptor Table (IDT). This is a bogus address as this
  * section will be stripped off in the final image.
@@ -135,11 +133,6 @@
 #define SRAM_REG_FW_END \
 	(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + (PLATFORM_CORE_COUNT - 1) * 0x4)
 
-/* Host page size */
-#define HOST_PAGE_SIZE		4096
-
-#define SRAM_BANK_SIZE                  (64 * 1024)
-
 /* low power ram where DMA buffers are typically placed */
 #define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
 #define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
index 2225f268fb8..ff7e7d1dfb6 100644
--- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
@@ -21,8 +21,6 @@
 #define RAM_SIZE \
 	(L2_SRAM_SIZE - HP_RAM_RESERVE_HEADER_SPACE - VECTOR_TBL_SIZE)
 
-#define LPSRAM_MASK(x)		0x00000003
-
 /* Location for the intList section which is later used to construct the
  * Interrupt Descriptor Table (IDT). This is a bogus address as this
  * section will be stripped off in the final image.
@@ -32,8 +30,6 @@
 /* size of the Interrupt Descriptor Table (IDT) */
 #define IDT_SIZE				0x2000
 
-#define SRAM_BANK_SIZE	(64 * 1024)
-
 /* boot loader in IMR */
 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE	0xB0038000
 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE	0x120
@@ -135,9 +131,6 @@
 	(SRAM_REG_FW_TRACEP_SLAVE_CORE_BASE + \
 	 (PLATFORM_CORE_COUNT - 1) * 0x4)
 
-/* Host page size */
-#define HOST_PAGE_SIZE		4096
-
 /* low power RAM where DMA buffers are typically placed, used by linker.ld */
 #define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
 #define LP_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
index c32e7e9d137..63730e4b7eb 100644
--- a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
+++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
@@ -20,6 +20,10 @@
 #include "platform.h"
 #include "manifest.h"
 
+#define LPSRAM_MASK(x) 0x00000003
+#define SRAM_BANK_SIZE (64 * 1024)
+#define HOST_PAGE_SIZE 4096
+
 #if CONFIG_SOC_INTEL_S1000
 #define MANIFEST_BASE	BOOT_LDR_MANIFEST_BASE
 #else