diff --git a/arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.mkw40z4 b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.mkw40z4
new file mode 100644
index 00000000000..8e9f2266fd7
--- /dev/null
+++ b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.defconfig.mkw40z4
@@ -0,0 +1,60 @@
+# Kconfig - Kinetis KWx SoC configuration options
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_MKW40Z4
+
+config SOC
+	string
+	default mkw40z4
+
+config NUM_IRQS
+	int
+	default 32
+
+if PINMUX
+
+config PINMUX_MCUX
+	def_bool y
+
+endif # PINMUX
+
+if GPIO
+
+config GPIO_MCUX
+	def_bool y
+
+endif # GPIO
+
+if SERIAL
+
+config UART_MCUX_LPUART
+	def_bool y
+
+endif # SERIAL
+
+if I2C
+
+config I2C_MCUX
+	def_bool y
+
+endif # I2C
+
+if RANDOM_GENERATOR
+
+config RANDOM_MCUX_TRNG
+	def_bool y
+
+endif # RANDOM_GENERATOR
+
+if FLASH
+
+config SOC_FLASH_MCUX
+	def_bool y
+
+endif # FLASH
+
+endif # SOC_MKW40Z4
diff --git a/arch/arm/soc/nxp_kinetis/kwx/Kconfig.soc b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.soc
index 71e8e230896..e881b65ad1d 100644
--- a/arch/arm/soc/nxp_kinetis/kwx/Kconfig.soc
+++ b/arch/arm/soc/nxp_kinetis/kwx/Kconfig.soc
@@ -9,6 +9,16 @@ choice
 prompt "Kinetis KWx MCU Selection"
 depends on SOC_SERIES_KINETIS_KWX
 
+config SOC_MKW40Z4
+	bool "SOC_MKW40Z4"
+	select CPU_CORTEX_M0PLUS
+	select HAS_MCUX
+	select HAS_OSC
+	select HAS_MCG
+	select HAS_LPUART
+	select HAS_TRNG
+	select HAS_SEGGER_RTT
+
 config SOC_MKW41Z4
 	bool "SOC_MKW41Z4"
 	select CPU_CORTEX_M0PLUS
@@ -22,6 +32,9 @@ endchoice
 
 if SOC_SERIES_KINETIS_KWX
 
+config SOC_PART_NUMBER_MKW40Z160VHT4
+	bool
+
 config SOC_PART_NUMBER_MKW41Z256VHT4
 	bool
 
@@ -30,6 +43,7 @@ config SOC_PART_NUMBER_MKW41Z512VHT4
 
 config SOC_PART_NUMBER_KINETIS_KWX
 	string
+	default "MKW40Z160VHT4" if SOC_PART_NUMBER_MKW40Z160VHT4
 	default "MKW41Z256VHT4" if SOC_PART_NUMBER_MKW41Z256VHT4
 	default "MKW41Z512VHT4" if SOC_PART_NUMBER_MKW41Z512VHT4
 	help
diff --git a/dts/arm/nxp/nxp_kw40z.dtsi b/dts/arm/nxp/nxp_kw40z.dtsi
new file mode 100644
index 00000000000..b6225d2facc
--- /dev/null
+++ b/dts/arm/nxp/nxp_kw40z.dtsi
@@ -0,0 +1,185 @@
+#include "armv6-m.dtsi"
+
+/ {
+	cpus {
+		cpu@0 {
+			compatible = "arm,cortex-m0+";
+		};
+	};
+
+	sram0: memory {
+		compatible = "mmio-sram";
+		reg = <0x20000000 0x4000>;
+	};
+
+	soc {
+		mcg: clock-controller@40064000 {
+			compatible = "nxp,kw41z-mcg";
+			reg = <0x40064000 0x13>;
+			system-clock-frequency = <48000000>;
+			clock-controller;
+		};
+
+		clock-controller@40065000 {
+			compatible = "nxp,kw41z-osc";
+			reg = <0x40065000 0x4>;
+			enable-external-reference;
+		};
+
+		rtc@4003d000 {
+			compatible = "nxp,kw41z-rtc";
+			reg = <0x4003d000 0x20>;
+			clock-frequency = <32768>;
+		};
+
+		sim: sim@40047000 {
+			compatible = "nxp,kw41z-sim";
+			reg = <0x40047000 0x1060>;
+
+			clock-controller;
+			#clock-cells = <2>;
+		};
+
+		flash0: flash@0 {
+			reg = <0 0x80000>;
+		};
+
+		lpuart0: lpuart@40054000 {
+			compatible = "nxp,kw41z-lpuart";
+			reg = <0x40054000 0x18>;
+			interrupts = <12 0>;
+
+			pinctrl-0 = <&lpuart0_default>;
+			pinctrl-names = "default";
+
+			status = "disabled";
+		};
+
+		pinmux_a: pinmux@40049000 {
+			compatible = "nxp,kw41z-pinmux";
+			reg = <0x40049000 0xa4>;
+			clocks = <&sim 0x1038 9>;
+
+			spi1_default: spi1_default {
+				mosi-miso-sck-pcs0 {
+					pins = <16>, <17>, <18>, <19>;
+					function = <2>;
+				};
+			};
+		};
+
+		pinmux_b: pinmux@4004a000 {
+			compatible = "nxp,kw41z-pinmux";
+			reg = <0x4004a000 0xa4>;
+			clocks = <&sim 0x1038 10>;
+		};
+
+		pinmux_c: pinmux@4004b000 {
+			compatible = "nxp,kw41z-pinmux";
+			reg = <0x4004b000 0xa4>;
+			clocks = <&sim 0x1038 11>;
+
+			lpuart0_default: lpuart0_default {
+				rx-tx {
+					pins = <6>, <7>;
+					function = <4>;
+				};
+			};
+
+			lpuart0_alt1: lpuart0_alt1 {
+				rx-tx {
+					pins = <17>, <18>;
+					function = <4>;
+				};
+			};
+
+			lpuart0_alt2: lpuart0_alt2 {
+				rx-tx-cts-rts {
+					pins = <2>, <3>, <0>, <1>;
+					function = <4>;
+				};
+			};
+
+			spi0_default: spi0_default {
+				mosi-miso-clk-pcs0 {
+					pins = <18>, <17>, <16>, <19>;
+					function = <2>;
+				};
+			};
+		};
+
+		gpioa: gpio@400ff000 {
+			compatible = "nxp,kw41z-gpio";
+			reg = <0x400ff000 0x40>;
+			interrupts = <30 2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpiob: gpio@400ff040 {
+			compatible = "nxp,kw41z-gpio";
+			reg = <0x400ff040 0x40>;
+			interrupts = <31 2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpioc: gpio@400ff080 {
+			compatible = "nxp,kw41z-gpio";
+			reg = <0x400ff080 0x40>;
+			interrupts = <31 2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		spi0: spi@4002c000 {
+			compatible = "nxp,kw41z-spi";
+			reg = <0x4002c000 0x9C>;
+			interrupts = <10 0>;
+			clocks = <&sim 0x103C 12>;		/* clk gate */
+
+			cs = <&gpiob 18 0>, <&gpiob 17 0>;
+			pinctrl-0 = <&spi0_default>;
+			pinctrl-names = "default";
+		};
+
+		spi1: spi@4002d000 {
+			compatible = "nxp,kw41z-spi";
+			reg = <0x4002d000 0x9C>;
+			interrupts = <29 0>;
+			clocks = <&sim 0x103C 13>;		/* clk gate */
+			status = "disabled";
+		};
+
+		pwm0: pwm@40038000 {
+			compatible = "nxp,kw41z-pwm";
+			reg = <0x40038000 0x88>;
+			prescaler = <2>;
+			period = <1000>;
+			clock-source = <0>;
+			/* channel information needed - fixme */
+		};
+
+		pwm1: pwm@40039000 {
+			compatible = "nxp,kw41z-pwm";
+			reg = <0x40039000 0x88>;
+			prescaler = <2>;
+			period = <1000>;
+			clock-source = <0>;
+			/* channel information needed - fixme */
+		};
+
+		pwm2: pwm@4003a000 {
+			compatible = "nxp,kw41z-pwm";
+			reg = <0x4003a000 0x88>;
+			prescaler = <2>;
+			period = <1000>;
+			clock-source = <0>;
+			/* channel information needed - fixme */
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <2>;
+};