boards: arm: Add Laird Connectivity BL5340 DVK platform
This adds initial support for the Laird Connectivity BL5340 development kit hardware Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
This commit is contained in:
Jamie McCrae
Ioannis Glaropoulos
parent
2de6bf91d5
commit
f4350a9303
28 changed files with 1480 additions and 3 deletions
9
boards/arm/bl5340_dvk/CMakeLists.txt
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9
boards/arm/bl5340_dvk/CMakeLists.txt
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@ -0,0 +1,9 @@
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# Copyright (c) 2019 Nordic Semiconductor ASA.
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# Copyright (c) 2021 Laird Connectivity.
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# SPDX-License-Identifier: Apache-2.0
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if ((CONFIG_BOARD_BL5340_DVK_CPUAPP OR CONFIG_BOARD_BL5340_DVK_CPUAPPNS)
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AND CONFIG_BOARD_ENABLE_CPUNET)
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zephyr_library()
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zephyr_library_sources(bl5340_dvk_cpunet_reset.c)
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endif()
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114
boards/arm/bl5340_dvk/Kconfig
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114
boards/arm/bl5340_dvk/Kconfig
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@ -0,0 +1,114 @@
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# BL5340-DVK board configuration
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# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA
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# Copyright (c) 2021 Laird Connectivity
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# SPDX-License-Identifier: Apache-2.0
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config IPM_NRFX
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default IPM
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config RPMSG_SERVICE_DUAL_IPM_SUPPORT
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default RPMSG_SERVICE
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if RPMSG_SERVICE_DUAL_IPM_SUPPORT
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config IPM_MSG_CH_0_ENABLE
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default y
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config IPM_MSG_CH_1_ENABLE
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default y
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config RPMSG_SERVICE_IPM_TX_NAME
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default "IPM_0" if RPMSG_SERVICE_MODE_MASTER
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default "IPM_1" if RPMSG_SERVICE_MODE_REMOTE
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config RPMSG_SERVICE_IPM_RX_NAME
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default "IPM_1" if RPMSG_SERVICE_MODE_MASTER
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default "IPM_0" if RPMSG_SERVICE_MODE_REMOTE
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config IPM_MSG_CH_0_TX
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default RPMSG_SERVICE_MODE_MASTER
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config IPM_MSG_CH_0_RX
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default RPMSG_SERVICE_MODE_REMOTE
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config IPM_MSG_CH_1_TX
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default RPMSG_SERVICE_MODE_REMOTE
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config IPM_MSG_CH_1_RX
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default RPMSG_SERVICE_MODE_MASTER
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endif # RPMSG_SERVICE_DUAL_IPM_SUPPORT
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if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPPNS
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config BOARD_ENABLE_DCDC_APP
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bool "Enable Application MCU DCDC converter"
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select SOC_DCDC_NRF53X_APP
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default y
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config BOARD_ENABLE_DCDC_NET
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bool "Enable Network MCU DCDC converter"
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select SOC_DCDC_NRF53X_NET
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default y
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config BOARD_ENABLE_DCDC_HV
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bool "Enable High Voltage DCDC converter"
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select SOC_DCDC_NRF53X_HV
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default y
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choice BT_HCI_BUS_TYPE
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default BT_RPMSG if BT
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endchoice
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config HEAP_MEM_POOL_SIZE
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default 4096 if BT_RPMSG
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config BT_HCI_VS
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default y if BT
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config BOARD_ENABLE_CPUNET
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bool "Enable nRF53 Network MCU"
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help
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This option enables releasing the Network 'force off' signal, which
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as a consequence will power up the Network MCU during system boot.
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Additionally, the option allocates GPIO pins that will be used by UARTE
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of the Network MCU.
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Note: GPIO pin allocation can only be configured by the secure Application
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MCU firmware, so when this option is used with the non-secure version of
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the board, the application needs to take into consideration, that the
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secure firmware image must already have configured GPIO allocation for the
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Network MCU.
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default y if (BT || NRF_802154_SER_HOST)
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config DOMAIN_CPUNET_BOARD
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string
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default "bl5340_dvk_cpunet" if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPPNS
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depends on BOARD_ENABLE_CPUNET
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help
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The board which will be used for CPUNET domain when creating a multi
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image application where one or more images should be located on
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another board. For example hci_rpmsg on the bl5340_dvk_cpunet for
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Bluetooth applications.
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endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPPNS
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if BOARD_BL5340_DVK_CPUNET
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# BT_CTLR depends on BT. When BT is enabled we should default to also
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# enabling the controller.
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config BT_CTLR
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default y if BT
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config BT_ECC
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default y if BT
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config DOMAIN_CPUAPP_BOARD
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string
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default "bl5340_dvk_cpuapp" if BOARD_BL5340_DVK_CPUNET
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help
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The board which will be used for CPUAPP domain when creating a multi
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image application where one or more images should be located on
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another board.
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endif # BOARD_BL5340_DVK_CPUNET
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18
boards/arm/bl5340_dvk/Kconfig.board
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18
boards/arm/bl5340_dvk/Kconfig.board
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@ -0,0 +1,18 @@
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# BL5340-DVK board configuration
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# Copyright (c) 2021 Laird Connectivity
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF5340_CPUAPP_QKAA
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config BOARD_BL5340_DVK_CPUAPP
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bool "BL5340-DVK (nRF5340) Application MCU"
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config BOARD_BL5340_DVK_CPUAPPNS
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bool "BL5340-DVK (nRF5340) Application MCU non-secure"
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endif # SOC_NRF5340_CPUAPP_QKAA
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config BOARD_BL5340_DVK_CPUNET
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bool "BL5340-DVK (nRF5340) Network MCU"
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depends on SOC_NRF5340_CPUNET_QKAA
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103
boards/arm/bl5340_dvk/Kconfig.defconfig
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103
boards/arm/bl5340_dvk/Kconfig.defconfig
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@ -0,0 +1,103 @@
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# BL5340-DVK board configuration
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# Copyright (c) 2019-2020 Nordic Semiconductor ASA
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# Copyright (c) 2021 Laird Connectivity
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPPNS
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config BOARD
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default "bl5340_dvk_cpuapp" if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPPNS
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config FLASH
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default y
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if BOARD_BL5340_DVK_CPUAPP
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# Enable QSPI for secondary partition maps
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config NORDIC_QSPI_NOR
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default y
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endif # BOARD_BL5340_DVK_CPUAPP
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# By default, if we build for a Non-Secure version of the board,
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# force building with TF-M as the Secure Execution Environment.
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config BUILD_WITH_TFM
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default y if BOARD_BL5340_DVK_CPUAPPNS
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if BUILD_WITH_TFM
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# By default, if we build with TF-M, instruct build system to
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# flash the combined TF-M (Secure) & Zephyr (Non Secure) image
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# (when building in-tree tests).
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config TFM_FLASH_MERGED_BINARY
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bool
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default y if TEST_ARM_CORTEX_M
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endif # BUILD_WITH_TFM
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# Code Partition:
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#
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# For the secure version of the board the firmware is linked at the beginning
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# of the flash, or into the code-partition defined in DT if it is intended to
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# be loaded by MCUboot. If the secure firmware is to be combined with a non-
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# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always
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# be restricted to the size of its code partition.
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#
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# For the non-secure version of the board, the firmware
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# must be linked into the code-partition (non-secure) defined in DT, regardless.
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# Apply this configuration below by setting the Kconfig symbols used by
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# the linker according to the information extracted from DT partitions.
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# SRAM Partition:
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#
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# If the secure firmware is to be combined with a non-secure image
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# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always
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# be restricted to the secure image SRAM partition (sram-secure-partition).
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# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram
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# may be used by the image.
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#
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# For the non-secure version of the board, the firmware image SRAM is
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# always restricted to the allocated non-secure SRAM partition.
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#
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
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DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
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if BOARD_BL5340_DVK_CPUAPP && TRUSTED_EXECUTION_SECURE
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config FLASH_LOAD_SIZE
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default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
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config SRAM_SIZE
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K)
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endif # BOARD_BL5340_DVK_CPUAPP && TRUSTED_EXECUTION_SECURE
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if BOARD_BL5340_DVK_CPUAPPNS
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config FLASH_LOAD_OFFSET
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
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config FLASH_LOAD_SIZE
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default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
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endif # BOARD_BL5340_DVK_CPUAPPNS
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if (BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPPNS) && USB
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config USB_NRFX
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default y
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config USB_DEVICE_STACK
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default y
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endif # (BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPPNS) && USB
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endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPPNS
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config BOARD
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default "bl5340_dvk_cpunet" if BOARD_BL5340_DVK_CPUNET
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27
boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts
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27
boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts
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/*
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* Copyright (c) 2021 Laird Connectivity
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
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#include "bl5340_dvk_cpuapp_common.dts"
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/ {
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model = "Laird Connectivity BL5340 (nRF5340) Application";
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compatible = "lairdconnectivity,bl5340-dvk-cpuapp";
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chosen {
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zephyr,sram = &sram0_image;
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zephyr,flash = &flash0;
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zephyr,code-partition = &slot0_partition;
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zephyr,sram-secure-partition = &sram0_s;
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zephyr,sram-non-secure-partition = &sram0_ns;
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};
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};
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&usbd {
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compatible = "nordic,nrf-usbd";
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status = "okay";
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};
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20
boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.yaml
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20
boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.yaml
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identifier: bl5340_dvk_cpuapp
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name: BL5340-DVK-application-MCU
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type: mcu
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arch: arm
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toolchain:
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- gnuarmemb
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- xtools
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- zephyr
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ram: 448
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flash: 1024
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supported:
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- gpio
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- i2c
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- pwm
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- qspi
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- spi
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- watchdog
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- uart
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- usb_cdc
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- usb_device
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275
boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dts
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275
boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dts
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/*
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* Copyright (c) 2019-2020 Nordic Semiconductor ASA
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* Copyright (c) 2021 Laird Connectivity
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,uart-mcumgr = &uart0;
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zephyr,bt-mon-uart = &uart0;
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zephyr,bt-c2h-uart = &uart0;
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};
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buttons {
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compatible = "gpio-keys";
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boot_button0: boot_button {
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gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
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label = "Bootloader button S4";
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};
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};
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/* These aliases are provided for compatibility with samples */
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aliases {
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sw0 = &boot_button0;
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};
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};
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&adc {
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status = "okay";
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};
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&gpiote {
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status = "okay";
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&i2c1 {
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compatible = "nordic,nrf-twim";
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status = "okay";
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sda-pin = <34>;
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scl-pin = <35>;
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at24c256@50 {
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compatible = "atmel,at24";
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reg = <0x50>;
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label = "EEPROM";
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size = <32768>;
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pagesize = <64>;
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address-width = <16>;
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timeout = <10>;
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};
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lis3dh@18 {
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compatible = "st,lis2dh";
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label = "LIS3DH";
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reg = <0x18>;
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irq-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>, <&gpio0 24 GPIO_ACTIVE_LOW>;
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};
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ft5336@38 {
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compatible = "focaltech,ft5336";
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reg = <0x38>;
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label = "TOUCH";
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int-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
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};
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bme680@76 {
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compatible = "bosch,bme680";
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reg = <0x76>;
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label = "BME680";
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};
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};
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&spi2 {
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compatible = "nordic,nrf-spim";
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status = "okay";
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cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
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miso-pin = <26>;
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mosi-pin = <27>;
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sck-pin = <28>;
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enc424j600@0 {
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compatible = "microchip,enc424j600";
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reg = <0>;
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spi-max-frequency = <8000000>;
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label = "ETHERNET";
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int-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
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};
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};
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&spi3 {
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compatible = "nordic,nrf-spim";
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status = "okay";
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sck-pin = <46>;
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miso-pin = <47>;
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mosi-pin = <45>;
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cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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sdhc@0 {
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compatible = "zephyr,mmc-spi-slot";
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reg = <0>;
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status = "okay";
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label = "SDHC";
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spi-max-frequency = <8000000>;
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};
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};
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&spi4 {
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compatible = "nordic,nrf-spim";
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status = "okay";
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cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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miso-pin = <10>;
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mosi-pin = <9>;
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sck-pin = <8>;
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ili9340@0 {
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compatible = "ilitek,ili9340";
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reg = <0>;
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spi-max-frequency = <32000000>;
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label = "DISPLAY";
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reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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cmd-data-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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rotation = <270>;
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};
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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tx-pin = <20>;
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rx-pin = <22>;
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rts-pin = <19>;
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cts-pin = <21>;
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};
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&pwm0 {
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status = "okay";
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ch0-pin = <28>;
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};
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&timer0 {
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status = "okay";
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};
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&timer1 {
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status = "okay";
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};
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&timer2 {
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status = "okay";
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};
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&qspi {
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status = "okay";
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sck-pin = <17>;
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io-pins = <13>, <14>, <15>, <16>;
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csn-pins = <18>;
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mx25r64: mx25r6435f@0 {
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compatible = "nordic,qspi-nor";
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reg = <0>;
|
||||
/* MX24R64 supports only pp and pp4io */
|
||||
writeoc = "pp4io";
|
||||
/* MX24R64 supports all readoc options */
|
||||
readoc = "read4io";
|
||||
sck-frequency = <8000000>;
|
||||
label = "MX25R64";
|
||||
jedec-id = [c2 28 17];
|
||||
sfdp-bfp = [
|
||||
e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
|
||||
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
|
||||
10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44
|
||||
30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
|
||||
];
|
||||
size = <67108864>;
|
||||
has-dpd;
|
||||
t-enter-dpd = <10000>;
|
||||
t-exit-dpd = <35000>;
|
||||
};
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* 64K */
|
||||
boot_partition: partition@0 {
|
||||
label = "mcuboot";
|
||||
reg = <0x00000000 0x00010000>;
|
||||
};
|
||||
/* 640K */
|
||||
slot0_partition: partition@10000 {
|
||||
label = "image-0";
|
||||
};
|
||||
/* 256K */
|
||||
slot0_ns_partition: partition@b0000 {
|
||||
label = "image-0-nonsecure";
|
||||
};
|
||||
|
||||
/*
|
||||
* The flash starting at 0x000f8000 and ending at
|
||||
* 0x000fffff is reserved for use by the application.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Storage partition will be used by FCB/NVS
|
||||
* if enabled. 32K
|
||||
*/
|
||||
storage_partition: partition@f8000 {
|
||||
label = "storage";
|
||||
reg = <0x000f8000 0x00008000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mx25r64 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* 640K */
|
||||
slot1_partition: partition@0 {
|
||||
label = "image-1";
|
||||
};
|
||||
/* 256K */
|
||||
slot1_ns_partition: partition@A0000 {
|
||||
label = "image-1-nonsecure";
|
||||
};
|
||||
/* 128K */
|
||||
scratch_partition: partition@e0000 {
|
||||
label = "image-scratch";
|
||||
reg = <0x000e0000 0x00020000>;
|
||||
};
|
||||
/* 7MB */
|
||||
lfs_partition: partition@100000 {
|
||||
label = "lfs_storage";
|
||||
reg = <0x00100000 0x000700000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/ {
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
sram0_image: image@20000000 {
|
||||
/* Zephyr image(s) memory */
|
||||
};
|
||||
|
||||
sram0_s: image_s@20000000 {
|
||||
/* Secure image memory */
|
||||
};
|
||||
|
||||
sram0_ns: image_ns@20040000 {
|
||||
/* Non-Secure image memory */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Include partition configuration file */
|
||||
#include "bl5340_dvk_cpuapp_partition_conf.dts"
|
||||
24
boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig
Normal file
24
boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
CONFIG_SOC_SERIES_NRF53X=y
|
||||
CONFIG_SOC_NRF5340_CPUAPP_QKAA=y
|
||||
CONFIG_BOARD_BL5340_DVK_CPUAPP=y
|
||||
|
||||
# Enable MPU
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
# Enable hardware stack protection
|
||||
CONFIG_HW_STACK_PROTECTION=y
|
||||
|
||||
# Enable TrustZone-M
|
||||
CONFIG_ARM_TRUSTZONE_M=y
|
||||
|
||||
# enable GPIO
|
||||
CONFIG_GPIO=y
|
||||
|
||||
# Enable uart driver
|
||||
CONFIG_SERIAL=y
|
||||
|
||||
# enable console
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
61
boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_partition_conf.dts
Normal file
61
boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_partition_conf.dts
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2020 Nordic Semiconductor ASA
|
||||
* Copyright (c) 2021 Laird Connectivity
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*
|
||||
* Default Flash planning for bl5340_dvk CPUAPP (Application MCU).
|
||||
*
|
||||
* Zephyr build for BL5340 with ARM TrustZone-M support,
|
||||
* implies building Secure and Non-Secure Zephyr images.
|
||||
*
|
||||
* Secure image will be placed, by default, in flash0
|
||||
* (or in slot0, if MCUboot is present).
|
||||
* Secure image will use sram0 for system memory.
|
||||
*
|
||||
* Non-Secure image will be placed in slot0_ns, and use
|
||||
* sram0_ns for system memory.
|
||||
*
|
||||
* Note that the Secure image only requires knowledge of
|
||||
* the beginning of the Non-Secure image (not its size).
|
||||
*/
|
||||
|
||||
&slot0_partition {
|
||||
reg = <0x00010000 0xa0000>;
|
||||
};
|
||||
|
||||
&slot0_ns_partition {
|
||||
reg = <0x000b0000 0x40000>;
|
||||
};
|
||||
|
||||
&slot1_partition {
|
||||
reg = <0x00000000 0xa0000>;
|
||||
};
|
||||
|
||||
&slot1_ns_partition {
|
||||
reg = <0x000a0000 0x40000>;
|
||||
};
|
||||
|
||||
/* Default SRAM planning when building for nRF5340 with
|
||||
* ARM TrustZone-M support
|
||||
* - Lowest 256 kB SRAM allocated to Secure image (sram0_s)
|
||||
* - Middle 192 kB allocated to Non-Secure image (sram0_ns)
|
||||
* - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
|
||||
* (see bl5340_dvk_shared_sram_planning_conf.dts)
|
||||
*/
|
||||
&sram0_image {
|
||||
reg = <0x20000000 DT_SIZE_K(448)>;
|
||||
};
|
||||
|
||||
&sram0_s {
|
||||
reg = <0x20000000 0x40000>;
|
||||
};
|
||||
|
||||
&sram0_ns {
|
||||
reg = <0x20040000 0x30000>;
|
||||
};
|
||||
|
||||
/* Include shared RAM configuration file */
|
||||
#include "bl5340_dvk_shared_sram_planning_conf.dts"
|
||||
25
boards/arm/bl5340_dvk/bl5340_dvk_cpuappns.dts
Normal file
25
boards/arm/bl5340_dvk/bl5340_dvk_cpuappns.dts
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Laird Connectivity
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <nordic/nrf5340_cpuappns_qkaa.dtsi>
|
||||
#include "bl5340_dvk_cpuapp_common.dts"
|
||||
|
||||
/ {
|
||||
model = "Laird Connectivity BL5340 (nRF5340) Application";
|
||||
compatible = "lairdconnectivity,bl5340-dvk-cpuapp";
|
||||
|
||||
chosen {
|
||||
zephyr,sram = &sram0_ns;
|
||||
zephyr,flash = &flash0;
|
||||
zephyr,code-partition = &slot0_ns_partition;
|
||||
};
|
||||
};
|
||||
|
||||
&usbd {
|
||||
compatible = "nordic,nrf-usbd";
|
||||
status = "okay";
|
||||
};
|
||||
19
boards/arm/bl5340_dvk/bl5340_dvk_cpuappns.yaml
Normal file
19
boards/arm/bl5340_dvk/bl5340_dvk_cpuappns.yaml
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
identifier: bl5340_dvk_cpuappns
|
||||
name: BL5340-DVK-application-MCU-Non-Secure
|
||||
type: mcu
|
||||
arch: arm
|
||||
toolchain:
|
||||
- gnuarmemb
|
||||
- xtools
|
||||
- zephyr
|
||||
ram: 192
|
||||
flash: 192
|
||||
supported:
|
||||
- gpio
|
||||
- i2c
|
||||
- pwm
|
||||
- spi
|
||||
- watchdog
|
||||
- uart
|
||||
- usb_cdc
|
||||
- usb_device
|
||||
27
boards/arm/bl5340_dvk/bl5340_dvk_cpuappns_defconfig
Normal file
27
boards/arm/bl5340_dvk/bl5340_dvk_cpuappns_defconfig
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
CONFIG_SOC_SERIES_NRF53X=y
|
||||
CONFIG_SOC_NRF5340_CPUAPP_QKAA=y
|
||||
CONFIG_BOARD_BL5340_DVK_CPUAPPNS=y
|
||||
|
||||
# Enable MPU
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
# Enable hardware stack protection
|
||||
CONFIG_HW_STACK_PROTECTION=y
|
||||
|
||||
# Enable TrustZone-M
|
||||
CONFIG_ARM_TRUSTZONE_M=y
|
||||
|
||||
# This Board implies building Non-Secure firmware
|
||||
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
|
||||
|
||||
# enable GPIO
|
||||
CONFIG_GPIO=y
|
||||
|
||||
# Enable uart driver
|
||||
CONFIG_SERIAL=y
|
||||
|
||||
# enable console
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
98
boards/arm/bl5340_dvk/bl5340_dvk_cpunet.dts
Normal file
98
boards/arm/bl5340_dvk/bl5340_dvk_cpunet.dts
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Laird Connectivity
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <nordic/nrf5340_cpunet_qkaa.dtsi>
|
||||
|
||||
/ {
|
||||
model = "Laird Connectivity BL5340 (nRF5340) Network";
|
||||
compatible = "lairdconnectivity,bl5340-dvk-cpunet";
|
||||
|
||||
chosen {
|
||||
zephyr,console = &uart0;
|
||||
zephyr,shell-uart = &uart0;
|
||||
zephyr,uart-mcumgr = &uart0;
|
||||
zephyr,bt-mon-uart = &uart0;
|
||||
zephyr,bt-c2h-uart = &uart0;
|
||||
zephyr,sram = &sram1;
|
||||
zephyr,flash = &flash1;
|
||||
zephyr,code-partition = &slot0_partition;
|
||||
};
|
||||
};
|
||||
|
||||
&gpiote {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
current-speed = <115200>;
|
||||
tx-pin = <40>;
|
||||
rx-pin = <42>;
|
||||
rts-pin = <39>;
|
||||
cts-pin = <41>;
|
||||
};
|
||||
|
||||
&timer0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&timer1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&timer2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flash1 {
|
||||
/*
|
||||
* For more information, see:
|
||||
* http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions
|
||||
*/
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* 48K */
|
||||
boot_partition: partition@0 {
|
||||
label = "mcuboot";
|
||||
reg = <0x00000000 0xc000>;
|
||||
};
|
||||
/* 88K */
|
||||
slot0_partition: partition@c000 {
|
||||
label = "image-0";
|
||||
reg = <0x0000C000 0x16000>;
|
||||
};
|
||||
/* 88K */
|
||||
slot1_partition: partition@22000 {
|
||||
label = "image-1";
|
||||
reg = <0x00022000 0x16000>;
|
||||
};
|
||||
/* 12K */
|
||||
scratch_partition: partition@38000 {
|
||||
label = "image-scratch";
|
||||
reg = <0x00038000 0x3000>;
|
||||
};
|
||||
/* 20K */
|
||||
storage_partition: partition@3B000 {
|
||||
label = "storage";
|
||||
reg = <0x0003B000 0x5000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Include shared RAM configuration file */
|
||||
#include "bl5340_dvk_shared_sram_planning_conf.dts"
|
||||
15
boards/arm/bl5340_dvk/bl5340_dvk_cpunet.yaml
Normal file
15
boards/arm/bl5340_dvk/bl5340_dvk_cpunet.yaml
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
identifier: bl5340_dvk_cpunet
|
||||
name: BL5340-DVK-network-MCU
|
||||
type: mcu
|
||||
arch: arm
|
||||
toolchain:
|
||||
- gnuarmemb
|
||||
- xtools
|
||||
- zephyr
|
||||
ram: 64
|
||||
flash: 256
|
||||
supported:
|
||||
- gpio
|
||||
- i2c
|
||||
- spi
|
||||
- watchdog
|
||||
21
boards/arm/bl5340_dvk/bl5340_dvk_cpunet_defconfig
Normal file
21
boards/arm/bl5340_dvk/bl5340_dvk_cpunet_defconfig
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
CONFIG_SOC_SERIES_NRF53X=y
|
||||
CONFIG_SOC_NRF5340_CPUNET_QKAA=y
|
||||
CONFIG_BOARD_BL5340_DVK_CPUNET=y
|
||||
|
||||
# Enable MPU
|
||||
CONFIG_ARM_MPU=y
|
||||
|
||||
# Enable hardware stack protection
|
||||
CONFIG_HW_STACK_PROTECTION=y
|
||||
|
||||
# enable GPIO
|
||||
CONFIG_GPIO=y
|
||||
|
||||
# Enable uart driver
|
||||
CONFIG_SERIAL=y
|
||||
|
||||
# enable console
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
76
boards/arm/bl5340_dvk/bl5340_dvk_cpunet_reset.c
Normal file
76
boards/arm/bl5340_dvk/bl5340_dvk_cpunet_reset.c
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2021 Nordic Semiconductor ASA.
|
||||
* Copyright (c) 2021 Laird Connectivity
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr.h>
|
||||
#include <init.h>
|
||||
#include <logging/log.h>
|
||||
|
||||
#include <soc.h>
|
||||
|
||||
LOG_MODULE_REGISTER(bl5340_dvk_cpuapp, CONFIG_LOG_DEFAULT_LEVEL);
|
||||
|
||||
#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
|
||||
|
||||
/* This should come from DTS, possibly an overlay. */
|
||||
#if defined(CONFIG_BOARD_BL5340_DVK_CPUAPP)
|
||||
#define CPUNET_UARTE_PIN_TX 8
|
||||
#define CPUNET_UARTE_PIN_RX 10
|
||||
#define CPUNET_UARTE_PORT_TRX NRF_P1
|
||||
#define CPUNET_UARTE_PIN_RTS 7
|
||||
#define CPUNET_UARTE_PIN_CTS 9
|
||||
#define CPUNET_UARTE_PORT_RCTS NRF_P1
|
||||
#endif
|
||||
|
||||
static void remoteproc_mgr_config(void)
|
||||
{
|
||||
/* UARTE */
|
||||
/* Assign specific GPIOs that will be used to get UARTE from
|
||||
* nRF5340 Network MCU.
|
||||
*/
|
||||
CPUNET_UARTE_PORT_TRX->PIN_CNF[CPUNET_UARTE_PIN_TX] =
|
||||
GPIO_PIN_CNF_MCUSEL_NetworkMCU << GPIO_PIN_CNF_MCUSEL_Pos;
|
||||
CPUNET_UARTE_PORT_TRX->PIN_CNF[CPUNET_UARTE_PIN_RX] =
|
||||
GPIO_PIN_CNF_MCUSEL_NetworkMCU << GPIO_PIN_CNF_MCUSEL_Pos;
|
||||
CPUNET_UARTE_PORT_RCTS->PIN_CNF[CPUNET_UARTE_PIN_RTS] =
|
||||
GPIO_PIN_CNF_MCUSEL_NetworkMCU << GPIO_PIN_CNF_MCUSEL_Pos;
|
||||
CPUNET_UARTE_PORT_RCTS->PIN_CNF[CPUNET_UARTE_PIN_CTS] =
|
||||
GPIO_PIN_CNF_MCUSEL_NetworkMCU << GPIO_PIN_CNF_MCUSEL_Pos;
|
||||
|
||||
/* Retain nRF5340 Network MCU in Secure domain (bus
|
||||
* accesses by Network MCU will have Secure attribute set).
|
||||
*/
|
||||
NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4;
|
||||
}
|
||||
#endif /* !CONFIG_TRUSTED_EXECUTION_NONSECURE */
|
||||
|
||||
static int remoteproc_mgr_boot(const struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
|
||||
/* Secure domain may configure permissions for the Network MCU. */
|
||||
remoteproc_mgr_config();
|
||||
#endif /* !CONFIG_TRUSTED_EXECUTION_NONSECURE */
|
||||
|
||||
#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE)
|
||||
/*
|
||||
* Building Zephyr with CONFIG_TRUSTED_EXECUTION_SECURE=y implies
|
||||
* building also a Non-Secure image. The Non-Secure image will, in
|
||||
* this case do the remainder of actions to properly configure and
|
||||
* boot the Network MCU.
|
||||
*/
|
||||
|
||||
/* Release the Network MCU, 'Release force off signal' */
|
||||
NRF_RESET->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release;
|
||||
|
||||
LOG_DBG("Network MCU released.");
|
||||
#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
* Copyright (c) 2021 Laird Connectivity
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* Default shared SRAM planning when building for BL5340 DVK.
|
||||
* This file is included by both nRF5340 CPUAPP (Application MCU)
|
||||
* and nRF5340 CPUNET (Network MCU).
|
||||
* - 64 kB SRAM allocated as Shared memory (sram0_shared)
|
||||
* - Region defined after the image SRAM of Application MCU
|
||||
*/
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
/* shared memory reserved for the inter-processor communication */
|
||||
zephyr,ipc_shm = &sram0_shared;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
sram0_shared: memory@20070000 {
|
||||
/* SRAM allocated to shared memory */
|
||||
reg = <0x20070000 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
22
boards/arm/bl5340_dvk/board.cmake
Normal file
22
boards/arm/bl5340_dvk/board.cmake
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# Copyright (c) 2021 Laird Connectivity
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if(CONFIG_BOARD_BL5340_DVK_CPUAPPNS)
|
||||
set(TFM_PUBLIC_KEY_FORMAT "full")
|
||||
endif()
|
||||
|
||||
if(CONFIG_BOARD_BL5340_DVK_CPUAPP OR CONFIG_BOARD_BL5340_DVK_CPUAPPNS)
|
||||
board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
|
||||
endif()
|
||||
|
||||
if(CONFIG_TFM_FLASH_MERGED_BINARY)
|
||||
set_property(TARGET runners_yaml_props_target PROPERTY hex_file "${CMAKE_BINARY_DIR}/tfm_merged.hex")
|
||||
endif()
|
||||
|
||||
if(CONFIG_BOARD_BL5340_DVK_CPUNET)
|
||||
board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000")
|
||||
endif()
|
||||
|
||||
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
|
||||
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
|
||||
0
boards/arm/bl5340_dvk/doc/img/bl5340_dvk_front.jpg
Normal file
0
boards/arm/bl5340_dvk/doc/img/bl5340_dvk_front.jpg
Normal file
437
boards/arm/bl5340_dvk/doc/index.rst
Normal file
437
boards/arm/bl5340_dvk/doc/index.rst
Normal file
|
|
@ -0,0 +1,437 @@
|
|||
.. _bl5340_dvk:
|
||||
|
||||
Laird Connectivity BL5340 DVK
|
||||
#############################
|
||||
|
||||
Overview
|
||||
********
|
||||
The BL5340 Development Kit provides support for the Laird Connectivity
|
||||
BL5340 module which is powered by a dual-core Nordic Semiconductor
|
||||
nRF5340 ARM Cortex-M33F CPU. The nRF5340 inside the BL5340 module is a
|
||||
dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
|
||||
|
||||
* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
|
||||
Armv8-M Security Extension, running at up to 128 MHz, referred to as
|
||||
the **application core**
|
||||
* a secondary Arm Cortex-M33 core, with a reduced feature set, running
|
||||
at a fixed 64 MHz, referred to as the **network core**.
|
||||
|
||||
The bl5340_dvk_cpuapp build target provides support for the application
|
||||
core on the BL5340 module. The bl5340_dvk_cpunet build target provides
|
||||
support for the network core on the BL5340 module. If ARM TrustZone is
|
||||
used then the bl5340_dvk_cpuapp build target provides support for the
|
||||
non-secure partition of the application core on the BL5340 module.
|
||||
|
||||
This development kit has the following features:
|
||||
|
||||
* :abbr:`ADC (Analog to Digital Converter)`
|
||||
* CLOCK
|
||||
* FLASH
|
||||
* :abbr:`GPIO (General Purpose Input Output)`
|
||||
* :abbr:`IDAU (Implementation Defined Attribution Unit)`
|
||||
* :abbr:`I2C (Inter-Integrated Circuit)`
|
||||
* :abbr:`I2S (Inter-Integrated Sound)`
|
||||
* :abbr:`MPU (Memory Protection Unit)`
|
||||
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
|
||||
* :abbr:`PWM (Pulse Width Modulation)`
|
||||
* :abbr:`QSPI (Quad Serial Peripheral Interface)`
|
||||
* RADIO (Bluetooth Low Energy and 802.15.4)
|
||||
* :abbr:`RTC (nRF RTC System Clock)`
|
||||
* Segger RTT (RTT Console)
|
||||
* :abbr:`SPI (Serial Peripheral Interface)`
|
||||
* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
|
||||
* :abbr:`USB (Universal Serial Bus)`
|
||||
* :abbr:`WDT (Watchdog Timer)`
|
||||
|
||||
.. figure:: img/bl5340_dvk_front.jpg
|
||||
:width: 800px
|
||||
:align: center
|
||||
:alt: BL5340 DVK
|
||||
|
||||
BL5340 DVK (Credit: Laird Connectivity)
|
||||
|
||||
More information about the module can be found on the
|
||||
`BL5340 homepage`_.
|
||||
|
||||
The `Nordic Semiconductor Infocenter`_
|
||||
contains the processor's information and the datasheet.
|
||||
|
||||
Hardware
|
||||
********
|
||||
|
||||
The BL5340 DVK has two external oscillators. The frequency of
|
||||
the slow clock is 32.768KHz. The frequency of the main clock
|
||||
is 32MHz.
|
||||
|
||||
Supported Features
|
||||
==================
|
||||
|
||||
The bl5340_dvk_cpuapp board configuration supports the following
|
||||
hardware features:
|
||||
|
||||
+-----------+------------+----------------------+
|
||||
| Interface | Controller | Driver/Component |
|
||||
+===========+============+======================+
|
||||
| ADC | on-chip | adc |
|
||||
+-----------+------------+----------------------+
|
||||
| CLOCK | on-chip | clock_control |
|
||||
+-----------+------------+----------------------+
|
||||
| FLASH | on-chip | flash |
|
||||
+-----------+------------+----------------------+
|
||||
| GPIO | on-chip | gpio |
|
||||
+-----------+------------+----------------------+
|
||||
| I2C(M) | on-chip | i2c |
|
||||
+-----------+------------+----------------------+
|
||||
| MPU | on-chip | arch/arm |
|
||||
+-----------+------------+----------------------+
|
||||
| NVIC | on-chip | arch/arm |
|
||||
+-----------+------------+----------------------+
|
||||
| QSPI(M) | on-chip | nor |
|
||||
+-----------+------------+----------------------+
|
||||
| PWM | on-chip | pwm |
|
||||
+-----------+------------+----------------------+
|
||||
| RTC | on-chip | system clock |
|
||||
+-----------+------------+----------------------+
|
||||
| RTT | Segger | console |
|
||||
+-----------+------------+----------------------+
|
||||
| SPI(M/S) | on-chip | spi |
|
||||
+-----------+------------+----------------------+
|
||||
| SPU | on-chip | system protection |
|
||||
+-----------+------------+----------------------+
|
||||
| UARTE | on-chip | serial |
|
||||
+-----------+------------+----------------------+
|
||||
| USB | on-chip | usb |
|
||||
+-----------+------------+----------------------+
|
||||
| WDT | on-chip | watchdog |
|
||||
+-----------+------------+----------------------+
|
||||
|
||||
The bl5340_dvk_cpunet board configuration supports the following
|
||||
hardware features:
|
||||
|
||||
+-----------+------------+----------------------+
|
||||
| Interface | Controller | Driver/Component |
|
||||
+===========+============+======================+
|
||||
| CLOCK | on-chip | clock_control |
|
||||
+-----------+------------+----------------------+
|
||||
| FLASH | on-chip | flash |
|
||||
+-----------+------------+----------------------+
|
||||
| GPIO | on-chip | gpio |
|
||||
+-----------+------------+----------------------+
|
||||
| I2C(M) | on-chip | i2c |
|
||||
+-----------+------------+----------------------+
|
||||
| MPU | on-chip | arch/arm |
|
||||
+-----------+------------+----------------------+
|
||||
| NVIC | on-chip | arch/arm |
|
||||
+-----------+------------+----------------------+
|
||||
| RADIO | on-chip | Bluetooth, |
|
||||
| | | ieee802154 |
|
||||
+-----------+------------+----------------------+
|
||||
| RTC | on-chip | system clock |
|
||||
+-----------+------------+----------------------+
|
||||
| RTT | Segger | console |
|
||||
+-----------+------------+----------------------+
|
||||
| SPI(M/S) | on-chip | spi |
|
||||
+-----------+------------+----------------------+
|
||||
| UARTE | on-chip | serial |
|
||||
+-----------+------------+----------------------+
|
||||
| WDT | on-chip | watchdog |
|
||||
+-----------+------------+----------------------+
|
||||
|
||||
Other hardware features are not supported by the Zephyr kernel.
|
||||
See `Nordic Semiconductor Infocenter`_
|
||||
for a complete list of hardware features.
|
||||
|
||||
Connections and IOs
|
||||
===================
|
||||
|
||||
An eight-pin GPIO port expander is used to provide additional inputs
|
||||
and outputs to the BL5340 module.
|
||||
|
||||
Refer to the `TI TCA9538 datasheet`_ for further details.
|
||||
|
||||
LEDs
|
||||
----
|
||||
|
||||
* LED1 (blue) = via TCA9538 port expander channel P4 (active low)
|
||||
* LED2 (blue) = via TCA9538 port expander channel P5 (active low)
|
||||
* LED3 (blue) = via TCA9538 port expander channel P6 (active low)
|
||||
* LED4 (blue) = via TCA9538 port expander channel P7 (active low)
|
||||
|
||||
Push buttons
|
||||
------------
|
||||
|
||||
* BUTTON1 = SW1 = via TCA9538 port expander channel P0 (active low)
|
||||
* BUTTON2 = SW2 = via TCA9538 port expander channel P1 (active low)
|
||||
* BUTTON3 = SW3 = via TCA9538 port expander channel P2 (active low)
|
||||
* BUTTON4 = SW4 = via TCA9538 port expander channel P3 (active low)
|
||||
* BOOT = boot (active low)
|
||||
|
||||
External Memory
|
||||
===============
|
||||
|
||||
Several external memory sources are available for the BL5340 DVK. These
|
||||
are described as follows.
|
||||
|
||||
Flash Memory
|
||||
------------
|
||||
|
||||
A Macronix MX25R6435FZNIL0 8MB external QSPI Flash memory part is
|
||||
incorporated for application image storage and large datasets.
|
||||
|
||||
Refer to the `Macronix MX25R6435FZNIL0 datasheet`_ for further details.
|
||||
|
||||
EEPROM Memory
|
||||
-------------
|
||||
|
||||
A 32KB Giantec GT24C256C-2GLI-TR EEPROM is available via I2C for
|
||||
storage of infrequently updated data and small datasets.
|
||||
|
||||
Refer to the `Giantec GT24C256C-2GLI-TR datasheet`_ for further details.
|
||||
|
||||
External Memory
|
||||
---------------
|
||||
|
||||
An on-board micro SD card slot is available for use with micro SD cards.
|
||||
|
||||
Sensors
|
||||
=======
|
||||
|
||||
The BL5340 DVK incorporates two sensors for user application testing.
|
||||
These are described as follows.
|
||||
|
||||
Temperature, Pressure, Humidity & Air Quality Sensor
|
||||
----------------------------------------------------
|
||||
|
||||
A Bosch BME680 Temperature, Pressure, Humidity & Air Quality sensor is
|
||||
available via I2C for environmental measurement applications.
|
||||
|
||||
Refer to the `Bosch BME680 datasheet`_ for further details.
|
||||
|
||||
3-Axis Accelerometer
|
||||
--------------------
|
||||
|
||||
An ST Microelectronics LIS3DH 3-Axis Accelerometer is available via I2C
|
||||
for vibration and motion detection applications.
|
||||
|
||||
Refer to the `ST Microelectronics LIS3DH datasheet`_ for further details.
|
||||
|
||||
Ethernet
|
||||
========
|
||||
|
||||
Cabled 10/100 Base-T Ethernet Connectivity is available via a Microchip
|
||||
ENC424J600 Ethernet controller.
|
||||
|
||||
Refer to the `Microchip ENC424J600 datasheet`_ for further details.
|
||||
|
||||
TFT Display & Capacitive Touch Screen Controller
|
||||
================================================
|
||||
|
||||
A 2.8 inch, 240 x 320 pixel TFT display with capacitive touch
|
||||
controller is included with the BL5340 DVK for user interface
|
||||
application features.
|
||||
|
||||
Refer to the `ER_TFTM028_4 datasheet`_ for a high level overview of the
|
||||
display.
|
||||
|
||||
An ILI9341 TFT controller is incorporated in the TFT module and
|
||||
acts as the main controller, controlled via SPI.
|
||||
|
||||
Refer to the `ILI9341 datasheet`_ for further details.
|
||||
|
||||
An FT6206 Capacitive Touch Controller, controlled via I2C is
|
||||
also incorporated in the TFT module.
|
||||
|
||||
Refer to the `FT6206 datasheet`_ for further details.
|
||||
|
||||
Real-Time Clock
|
||||
===============
|
||||
|
||||
A real-time clock is available for accurate time data availability.
|
||||
|
||||
Refer to the `Microchip MCP7940N datasheet`_ for further details.
|
||||
|
||||
DAC
|
||||
===
|
||||
|
||||
A 10-bit Digital to Analog Converter is incorporated for generation of
|
||||
variable voltages.
|
||||
|
||||
Refer to the `Microchip MCP4725 datasheet`_ for further details.
|
||||
|
||||
Security components
|
||||
===================
|
||||
|
||||
- Implementation Defined Attribution Unit (`IDAU`_) on the application
|
||||
core. The IDAU is implemented with the System Protection Unit and is
|
||||
used to define secure and non-secure memory maps. By default, all of
|
||||
the memory space (Flash, SRAM, and peripheral address space) is
|
||||
defined to be secure accessible only.
|
||||
- Secure boot.
|
||||
|
||||
Programming and Debugging
|
||||
*************************
|
||||
|
||||
The BL5340's application core supports the Armv8-M Security Extension.
|
||||
Applications built for the bl5340_dvk_cpuapp board by default
|
||||
boot in the Secure state.
|
||||
|
||||
The BL5340's network core does not support the Armv8-M Security
|
||||
Extension. The IDAU may configure bus accesses by the network core to
|
||||
have Secure attribute set; the latter allows to build and run Secure
|
||||
only applications on the BL5340 module.
|
||||
|
||||
Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg|
|
||||
=============================================================================
|
||||
|
||||
Applications on the BL5340 module may contain a Secure and a Non-Secure
|
||||
firmware image for the application core. The Secure image can be built
|
||||
using either Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure
|
||||
firmware images are always built using Zephyr. The two alternatives are
|
||||
described below.
|
||||
|
||||
.. note::
|
||||
|
||||
By default the the Secure image for BL5340's application core is
|
||||
built using TF-M.
|
||||
|
||||
Building the Secure firmware with TF-M
|
||||
--------------------------------------
|
||||
|
||||
The process to build the Secure firmware image using TF-M and the
|
||||
Non-Secure firmware image using Zephyr requires the following steps:
|
||||
|
||||
1. Build the Non-Secure Zephyr application
|
||||
for the application core using ``-DBOARD=bl5340_dvk_cpuappns``.
|
||||
To invoke the building of TF-M the Zephyr build system requires the
|
||||
Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by
|
||||
default when building Zephyr as a Non-Secure application.
|
||||
The Zephyr build system will perform the following steps automatically:
|
||||
|
||||
* Build the Non-Secure firmware image as a regular Zephyr application
|
||||
* Build a TF-M (secure) firmware image
|
||||
* Merge the output image binaries together
|
||||
* Optionally build a bootloader image (MCUboot)
|
||||
|
||||
.. note::
|
||||
|
||||
Depending on the TF-M configuration, an application DTS overlay may
|
||||
be required, to adjust the Non-Secure image Flash and SRAM starting
|
||||
address and sizes.
|
||||
|
||||
2. Build the application firmware for the network core using
|
||||
``-DBOARD=bl5340_dvk_cpunet``.
|
||||
|
||||
Building the Secure firmware using Zephyr
|
||||
-----------------------------------------
|
||||
|
||||
The process to build the Secure and the Non-Secure firmware images
|
||||
using Zephyr requires the following steps:
|
||||
|
||||
1. Build the Secure Zephyr application for the application core
|
||||
using ``-DBOARD=bl5340_dvk_cpuapp`` and
|
||||
``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n``
|
||||
in the application project configuration file.
|
||||
2. Build the Non-Secure Zephyr application for the application core
|
||||
using ``-DBOARD=bl5340_dvk_cpuappns``.
|
||||
3. Merge the two binaries together.
|
||||
4. Build the application firmware for the network core using
|
||||
``-DBOARD=bl5340_dvk_cpunet``.
|
||||
|
||||
When building a Secure/Non-Secure application for the BL5340's
|
||||
application core, the Secure application will have to set the IDAU
|
||||
(SPU) configuration to allow Non-Secure access to all CPU resources
|
||||
utilized by the Non-Secure application firmware. SPU configuration
|
||||
shall take place before jumping to the Non-Secure application.
|
||||
|
||||
Building a Secure only application
|
||||
==================================
|
||||
|
||||
Build the Zephyr app in the usual way (see :ref:`build_an_application`
|
||||
and :ref:`application_run`), using ``-DBOARD=bl5340_dvk_cpuapp`` for
|
||||
the firmware running on the BL5340's application core, and using
|
||||
``-DBOARD=bl5340_dvk_cpunet`` for the firmware running
|
||||
on the BL5340's network core.
|
||||
|
||||
Flashing
|
||||
========
|
||||
|
||||
Follow the instructions in the :ref:`nordic_segger` page to install
|
||||
and configure all the necessary software. Further information can be
|
||||
found in :ref:`nordic_segger_flashing`. Then you can build and flash
|
||||
applications as usual (:ref:`build_an_application` and
|
||||
:ref:`application_run` for more details).
|
||||
|
||||
.. warning::
|
||||
|
||||
The BL5340 has a flash read-back protection feature. When flash
|
||||
read-back protection is active, you will need to recover the chip
|
||||
before reflashing. If you are flashing with
|
||||
:ref:`west <west-build-flash-debug>`, run this command for more
|
||||
details on the related ``--recover`` option:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
west flash -H -r nrfjprog --skip-rebuild
|
||||
|
||||
.. note::
|
||||
|
||||
Flashing and debugging applications on the BL5340 DVK requires
|
||||
upgrading the nRF Command Line Tools to version 10.12.0 or newer.
|
||||
Further information on how to install the nRF Command Line Tools can
|
||||
be found in :ref:`nordic_segger_flashing`.
|
||||
|
||||
Here is an example for the :ref:`hello_world` application running on the
|
||||
BL5340's application core.
|
||||
|
||||
First, run your favorite terminal program to listen for output.
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
$ minicom -D <tty_device> -b 115200
|
||||
|
||||
Replace :code:`<tty_device>` with the port where the BL5340 DVK board
|
||||
can be found. For example, under Linux, :code:`/dev/ttyACM0`.
|
||||
|
||||
Then build and flash the application in the usual way.
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: bl5340_dvk_cpuapp
|
||||
:goals: build flash
|
||||
|
||||
Debugging
|
||||
=========
|
||||
|
||||
Refer to the :ref:`nordic_segger` page to learn about debugging
|
||||
boards with a Segger IC.
|
||||
|
||||
Testing Bluetooth on the BL5340 DVK
|
||||
***********************************
|
||||
Many of the Bluetooth examples will work on the BL5340 DVK.
|
||||
Try them out:
|
||||
|
||||
* :ref:`ble_peripheral`
|
||||
* :ref:`bluetooth-eddystone-sample`
|
||||
* :ref:`bluetooth-ibeacon-sample`
|
||||
|
||||
References
|
||||
**********
|
||||
|
||||
.. target-notes::
|
||||
|
||||
.. _IDAU:
|
||||
https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau
|
||||
.. _BL5340 homepage: https://www.lairdconnect.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl5340-series-multi-core-bluetooth-52-802154-nfc-modules
|
||||
.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com
|
||||
.. _TI TCA9538 datasheet: https://www.ti.com/lit/gpn/TCA9538
|
||||
.. _Macronix MX25R6435FZNIL0 datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7913/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.5.pdf
|
||||
.. _Giantec GT24C256C-2GLI-TR datasheet: http://www.giantec-semi.com/Upload/datasheet/CU/GT24C256C_DS_Cu.pdf
|
||||
.. _Bosch BME680 datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme680-ds001.pdf
|
||||
.. _ST Microelectronics LIS3DH datasheet: https://www.st.com/resource/en/datasheet/lis3dh.pdf
|
||||
.. _Microchip ENC424J600 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf
|
||||
.. _ER_TFTM028_4 datasheet: https://www.buydisplay.com/download/manual/ER-TFTM028-4_Datasheet.pdf
|
||||
.. _ILI9341 datasheet: https://www.buydisplay.com/download/ic/ILI9341.pdf
|
||||
.. _FT6206 datasheet: https://www.buydisplay.com/download/ic/FT6206.pdf
|
||||
.. _Microchip MCP7940N datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/20005010H.pdf
|
||||
.. _Microchip MCP4725 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22039d.pdf
|
||||
.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/
|
||||
8
boards/arm/bl5340_dvk/pre_dt_board.cmake
Normal file
8
boards/arm/bl5340_dvk/pre_dt_board.cmake
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# Copyright (c) 2021 Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
|
||||
# - flash-controller@39000 & kmu@39000
|
||||
# - power@5000 & clock@5000
|
||||
# - /reserved-memory/image@20000000 & /reserved-memory/image_s@20000000
|
||||
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
|
||||
|
|
@ -17,6 +17,7 @@ config TFM_BOARD
|
|||
default "stm/stm32l562e_dk" if BOARD_STM32L562E_DK
|
||||
default "musca_b1/sse_200" if BOARD_MUSCA_B1
|
||||
default "musca_s1" if BOARD_MUSCA_S1
|
||||
default "lairdconnectivity/bl5340_dvk_cpuapp" if BOARD_BL5340_DVK_CPUAPPNS
|
||||
help
|
||||
The board name used for building TFM. Building with TFM requires that
|
||||
TFM has been ported to the given board/SoC.
|
||||
|
|
|
|||
|
|
@ -4,5 +4,6 @@ tests:
|
|||
sample.usb.hid-mouse:
|
||||
depends_on: usb_device gpio
|
||||
harness: button
|
||||
filter: dt_alias_exists("sw0")
|
||||
filter: dt_alias_exists("sw0") and
|
||||
dt_alias_exists("led0")
|
||||
tags: usb
|
||||
|
|
|
|||
|
|
@ -184,6 +184,28 @@ Finally, flash the concatenated TF-M + Zephyr binary.
|
|||
|
||||
ninja flash
|
||||
|
||||
On BL5340:
|
||||
==========
|
||||
|
||||
Build Zephyr with a non-secure configuration
|
||||
(``-DBOARD=bl5340_dvk_cpuappns``).
|
||||
|
||||
Example using ``cmake`` and ``ninja``
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
cd <ZEPHYR_ROOT>/samples/tfm_integration/psa_level_1/
|
||||
rm -rf build
|
||||
mkdir build && cd build
|
||||
cmake -GNinja -DBOARD=bl5340_dvk_cpuappns ..
|
||||
|
||||
Flash the concatenated TF-M + Zephyr binary.
|
||||
|
||||
Example using ``west``
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
west flash --hex-file tfm_merged.hex
|
||||
|
||||
Sample Output
|
||||
=============
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ tests:
|
|||
tags: introduction tfm
|
||||
platform_allow: mps2_an521_nonsecure lpcxpresso55s69_ns nrf5340dk_nrf5340_cpuappns
|
||||
nrf9160dk_nrf9160ns nucleo_l552ze_q_ns v2m_musca_s1_nonsecure stm32l562e_dk_ns
|
||||
bl5340_dvk_cpuappns
|
||||
harness: console
|
||||
harness_config:
|
||||
type: multi_line
|
||||
|
|
|
|||
|
|
@ -199,6 +199,28 @@ Finally, flash the concatenated TF-M + Zephyr binary.
|
|||
|
||||
ninja flash
|
||||
|
||||
On BL5340:
|
||||
==========
|
||||
|
||||
Build Zephyr with a non-secure configuration
|
||||
(``-DBOARD=bl5340_dvk_cpuappns``).
|
||||
|
||||
Example using ``cmake`` and ``ninja``
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
cd <ZEPHYR_ROOT>/samples/tfm_integration/psa_level_1/
|
||||
rm -rf build
|
||||
mkdir build && cd build
|
||||
cmake -GNinja -DBOARD=bl5340_dvk_cpuappns ..
|
||||
|
||||
Flash the concatenated TF-M + Zephyr binary.
|
||||
|
||||
Example using ``west``
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
west flash --hex-file tfm_merged.hex
|
||||
|
||||
Sample Output
|
||||
=============
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ tests:
|
|||
tags: introduction tfm
|
||||
platform_allow: mps2_an521_nonsecure lpcxpresso55s69_ns
|
||||
nrf5340dk_nrf5340_cpuappns nrf9160dk_nrf9160ns nucleo_l552ze_q_ns
|
||||
stm32l562e_dk_ns v2m_musca_s1_nonsecure v2m_musca_b1_nonsecure
|
||||
stm32l562e_dk_ns v2m_musca_s1_nonsecure v2m_musca_b1_nonsecure bl5340_dvk_cpuappns
|
||||
harness: console
|
||||
harness_config:
|
||||
type: multi_line
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
common:
|
||||
tags: tfm
|
||||
platform_allow: mps2_an521_nonsecure v2m_musca_s1_nonsecure
|
||||
nrf5340dk_nrf5340_cpuappns nrf9160dk_nrf9160ns
|
||||
nrf5340dk_nrf5340_cpuappns nrf9160dk_nrf9160ns bl5340_dvk_cpuappns
|
||||
harness: console
|
||||
harness_config:
|
||||
type: multi_line
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue