From f42568ca7b5e5f426376ed1b37f5bb9325f4f339 Mon Sep 17 00:00:00 2001
From: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Date: Mon, 12 Aug 2024 13:39:53 +0300
Subject: [PATCH] soc: adi: Add the MAX78002 SoC

Added MAX78002 Kconfig and dts files.

Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
---
 dts/arm/adi/max32/max78002-pinctrl.dtsi  | 455 +++++++++++++++++++++++
 dts/arm/adi/max32/max78002.dtsi          | 211 +++++++++++
 soc/adi/max32/CMakeLists.txt             |   1 +
 soc/adi/max32/Kconfig                    |   3 +
 soc/adi/max32/Kconfig.defconfig          |   2 +-
 soc/adi/max32/Kconfig.defconfig.max78002 |  14 +
 soc/adi/max32/Kconfig.soc                |   9 +
 soc/adi/max32/max78002.ld                |  13 +
 soc/adi/max32/soc.yml                    |   3 +
 9 files changed, 710 insertions(+), 1 deletion(-)
 create mode 100644 dts/arm/adi/max32/max78002-pinctrl.dtsi
 create mode 100644 dts/arm/adi/max32/max78002.dtsi
 create mode 100644 soc/adi/max32/Kconfig.defconfig.max78002
 create mode 100644 soc/adi/max32/max78002.ld

diff --git a/dts/arm/adi/max32/max78002-pinctrl.dtsi b/dts/arm/adi/max32/max78002-pinctrl.dtsi
new file mode 100644
index 00000000000..7951d42dbcd
--- /dev/null
+++ b/dts/arm/adi/max32/max78002-pinctrl.dtsi
@@ -0,0 +1,455 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40008000 {
+
+			/omit-if-no-ref/ uart0a_rx_p0_0: uart0a_rx_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0a_tx_p0_1: uart0a_tx_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0a_ioa_p0_2: tmr0a_ioa_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0b_cts_p0_2: uart0b_cts_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ ext_clk_p0_3: ext_clk_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0b_rts_p0_3: uart0b_rts_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss0_p0_4: spi0_ss0_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0b_ioan_p0_4: tmr0b_ioan_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_mosi_p0_5: spi0_mosi_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0b_iobn_p0_5: tmr0b_iobn_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_miso_p0_6: spi0_miso_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ owm_io_p0_6: owm_io_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_sck_p0_7: spi0_sck_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ owm_pe_p0_7: owm_pe_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_sdio2_p0_8: spi0_sdio2_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0b_ioa_p0_8: tmr0b_ioa_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_sdio3_p0_9: spi0_sdio3_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0b_iob_p0_9: tmr0b_iob_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c0_scl_p0_10: i2c0_scl_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss2_p0_10: spi0_ss2_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c0_sda_p0_11: i2c0_sda_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss1_p0_11: spi0_ss1_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_rx_p0_12: uart1_rx_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1b_ioan_p0_12: tmr1b_ioan_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_tx_p0_13: uart1_tx_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1b_iobn_p0_13: tmr1b_iobn_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1a_ioa_p0_14: tmr1a_ioa_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2s_clkext_p0_14: i2s_clkext_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1a_iob_p0_15: tmr1a_iob_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_vsync_p0_15: pcif_vsync_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_p0_16: i2c1_scl_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt2_p0_16: pt2_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_p0_17: i2c1_sda_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt3_p0_17: pt3_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt0_p0_18: pt0_p0_18 {
+				pinmux = <MAX32_PINMUX(0, 18, AF1)>;
+			};
+
+			/omit-if-no-ref/ owm_io_p0_18: owm_io_p0_18 {
+				pinmux = <MAX32_PINMUX(0, 18, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt1_p0_19: pt1_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+			};
+
+			/omit-if-no-ref/ owm_pe_p0_19: owm_pe_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss0_p0_20: spi1_ss0_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d0_p0_20: pcif_d0_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_p0_21: spi1_mosi_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d1_p0_21: pcif_d1_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_miso_p0_22: spi1_miso_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d2_p0_22: pcif_d2_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_sck_p0_23: spi1_sck_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d3_p0_23: pcif_d3_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_sdio2_p0_24: spi1_sdio2_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d4_p0_24: pcif_d4_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_sdio3_p0_25: spi1_sdio3_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d5_p0_25: pcif_d5_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2_ioa_p0_26: tmr2_ioa_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d6_p0_26: pcif_d6_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2_iob_p0_27: tmr2_iob_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d7_p0_27: pcif_d7_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF2)>;
+			};
+
+			/omit-if-no-ref/ swdio_p0_28: swdio_p0_28 {
+				pinmux = <MAX32_PINMUX(0, 28, AF1)>;
+			};
+
+			/omit-if-no-ref/ swclk_p0_29: swclk_p0_29 {
+				pinmux = <MAX32_PINMUX(0, 29, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_p0_30: i2c2_scl_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d8_p0_30: pcif_d8_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_p0_31: i2c2_sda_p0_31 {
+				pinmux = <MAX32_PINMUX(0, 31, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d9_p0_31: pcif_d9_p0_31 {
+				pinmux = <MAX32_PINMUX(0, 31, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_rx_p1_0: uart2_rx_p1_0 {
+				pinmux = <MAX32_PINMUX(1, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tck_p1_0: rv_tck_p1_0 {
+				pinmux = <MAX32_PINMUX(1, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_tx_p1_1: uart2_tx_p1_1 {
+				pinmux = <MAX32_PINMUX(1, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tms_p1_1: rv_tms_p1_1 {
+				pinmux = <MAX32_PINMUX(1, 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s_sck_p1_2: i2s_sck_p1_2 {
+				pinmux = <MAX32_PINMUX(1, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tdi_p1_2: rv_tdi_p1_2 {
+				pinmux = <MAX32_PINMUX(1, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s_ws_p1_3: i2s_ws_p1_3 {
+				pinmux = <MAX32_PINMUX(1, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tdo_p1_3: rv_tdo_p1_3 {
+				pinmux = <MAX32_PINMUX(1, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s_sdi_p1_4: i2s_sdi_p1_4 {
+				pinmux = <MAX32_PINMUX(1, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr3b_ioa_p1_4: tmr3b_ioa_p1_4 {
+				pinmux = <MAX32_PINMUX(1, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s_sdo_p1_5: i2s_sdo_p1_5 {
+				pinmux = <MAX32_PINMUX(1, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr3b_iob_p1_5: tmr3b_iob_p1_5 {
+				pinmux = <MAX32_PINMUX(1, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3a_ioa_p1_6: tmr3a_ioa_p1_6 {
+				pinmux = <MAX32_PINMUX(1, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d10_p1_6: pcif_d10_p1_6 {
+				pinmux = <MAX32_PINMUX(1, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3a_iob_p1_7: tmr3a_iob_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d11_p1_7: pcif_d11_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ pcif_hsync_p1_8: pcif_hsync_p1_8 {
+				pinmux = <MAX32_PINMUX(1, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ rxev0_p1_8: rxev0_p1_8 {
+				pinmux = <MAX32_PINMUX(1, 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ pcif_pclk_p1_9: pcif_pclk_p1_9 {
+				pinmux = <MAX32_PINMUX(1, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ txev0_p1_9: txev0_p1_9 {
+				pinmux = <MAX32_PINMUX(1, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_cdn_p1_10: sdhc_cdn_p1_10 {
+				pinmux = <MAX32_PINMUX(1, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ adc_clk_ext_p1_10: adc_clk_ext_p1_10 {
+				pinmux = <MAX32_PINMUX(1, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat3_p1_11: sdhc_dat3_p1_11 {
+				pinmux = <MAX32_PINMUX(1, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat2_p1_12: sdhc_dat2_p1_12 {
+				pinmux = <MAX32_PINMUX(1, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ adc_hw_trig_a_p1_12: adc_hw_trig_a_p1_12 {
+				pinmux = <MAX32_PINMUX(1, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat1_p1_13: sdhc_dat1_p1_13 {
+				pinmux = <MAX32_PINMUX(1, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ adc_hw_trig_b_p1_13: adc_hw_trig_b_p1_13 {
+				pinmux = <MAX32_PINMUX(1, 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat0_p1_14: sdhc_dat0_p1_14 {
+				pinmux = <MAX32_PINMUX(1, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ adc_hw_trig_c_p1_14: adc_hw_trig_c_p1_14 {
+				pinmux = <MAX32_PINMUX(1, 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_wp_p1_15: sdhc_wp_p1_15 {
+				pinmux = <MAX32_PINMUX(1, 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ sdhc_cmd_p1_16: sdhc_cmd_p1_16 {
+				pinmux = <MAX32_PINMUX(1, 16, AF1)>;
+			};
+
+			/omit-if-no-ref/ sdhc_clk_p1_17: sdhc_clk_p1_17 {
+				pinmux = <MAX32_PINMUX(1, 17, AF1)>;
+			};
+
+			/omit-if-no-ref/ ain0_p2_0: ain0_p2_0 {
+				pinmux = <MAX32_PINMUX(2, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ ain1_p2_1: ain1_p2_1 {
+				pinmux = <MAX32_PINMUX(2, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ ain2_p2_2: ain2_p2_2 {
+				pinmux = <MAX32_PINMUX(2, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ ain3_p2_3: ain3_p2_3 {
+				pinmux = <MAX32_PINMUX(2, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ ain4_p2_4: ain4_p2_4 {
+				pinmux = <MAX32_PINMUX(2, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr0b_ioa_p2_4: lptmr0b_ioa_p2_4 {
+				pinmux = <MAX32_PINMUX(2, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain5_p2_5: ain5_p2_5 {
+				pinmux = <MAX32_PINMUX(2, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr1b_ioa_p2_5: lptmr1b_ioa_p2_5 {
+				pinmux = <MAX32_PINMUX(2, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain6_p2_6: ain6_p2_6 {
+				pinmux = <MAX32_PINMUX(2, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr0_clk_p2_6: lptmr0_clk_p2_6 {
+				pinmux = <MAX32_PINMUX(2, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ lpuartb_rx_p2_6: lpuartb_rx_p2_6 {
+				pinmux = <MAX32_PINMUX(2, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain7_p2_7: ain7_p2_7 {
+				pinmux = <MAX32_PINMUX(2, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr1_clk_p2_7: lptmr1_clk_p2_7 {
+				pinmux = <MAX32_PINMUX(2, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ lpuartb_tx_p2_7: lpuartb_tx_p2_7 {
+				pinmux = <MAX32_PINMUX(2, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ pdown_p3_0: pdown_p3_0 {
+				pinmux = <MAX32_PINMUX(3, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ wakeup_p3_0: wakeup_p3_0 {
+				pinmux = <MAX32_PINMUX(3, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ sqwout_p3_1: sqwout_p3_1 {
+				pinmux = <MAX32_PINMUX(3, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ wakeup_p3_1: wakeup_p3_1 {
+				pinmux = <MAX32_PINMUX(3, 1, AF2)>;
+			};
+
+		};
+	};
+};
diff --git a/dts/arm/adi/max32/max78002.dtsi b/dts/arm/adi/max32/max78002.dtsi
new file mode 100644
index 00000000000..0809d1b062c
--- /dev/null
+++ b/dts/arm/adi/max32/max78002.dtsi
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <adi/max32/max32xxx.dtsi>
+#include <zephyr/dt-bindings/dma/max78002_dma.h>
+
+&clk_ipo {
+	clock-frequency = <DT_FREQ_M(120)>;
+};
+
+&clk_inro {
+	clock-frequency = <DT_FREQ_K(30)>;
+};
+
+/delete-node/ &clk_erfo;
+
+/* MAX78002 extra clocks. */
+/ {
+	clocks {
+		clk_ipll: clk_ipll {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <DT_FREQ_M(100)>;
+			status = "disabled";
+		};
+
+		clk_ebo: clk_ebo {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <DT_FREQ_M(25)>;
+			status = "disabled";
+		};
+	};
+};
+
+&flash0 {
+	reg = <0x10000000 DT_SIZE_K(2560)>;
+	erase-block-size = <16384>;
+};
+
+&pinctrl {
+	reg = <0x40008000 0x2200>;
+
+	gpio2: gpio@40080400 {
+		reg = <0x40080400 0x200>;
+		compatible = "adi,max32-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <26 0>;
+		clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
+		status = "disabled";
+	};
+
+	gpio3: gpio@40080600 {
+		reg = <0x40080600 0x200>; // Address and size are dummy.
+		compatible = "adi,max32-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <54 0>;
+		status = "disabled";
+	};
+};
+
+&adc {
+	compatible = "adi,max32-adc-sar", "adi,max32-adc";
+	clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
+	clock-divider = <16>;
+	channel-count = <17>;
+	track-count = <4>;
+	idle-count = <0>;
+	vref-mv = <1250>;
+	resolution = <12>;
+};
+
+/* MAX78002 extra peripherals. */
+/ {
+	soc {
+		sram1: memory@20008000 {
+			compatible = "mmio-sram";
+			reg = <0x20008000 DT_SIZE_K(32)>;
+		};
+
+		sram2: memory@20010000 {
+			compatible = "mmio-sram";
+			reg = <0x20010000 DT_SIZE_K(64)>;
+		};
+
+		sram3: memory@20020000 {
+			compatible = "mmio-sram";
+			reg = <0x20020000 DT_SIZE_K(64)>;
+		};
+
+		sram4: memory@20030000 {
+			compatible = "mmio-sram";
+			reg = <0x20030000 DT_SIZE_K(64)>;
+		};
+
+		sram5: memory@20040000 {
+			compatible = "mmio-sram";
+			reg = <0x20040000 DT_SIZE_K(64)>;
+		};
+
+		sram6: memory@20050000 {
+			compatible = "mmio-sram";
+			reg = <0x20050000 DT_SIZE_K(48)>;
+		};
+
+		sram7: memory@2005c000 {
+			compatible = "mmio-sram";
+			reg = <0x2005c000 DT_SIZE_K(16)>;
+		};
+
+		uart3: serial@40081400 {
+			compatible = "adi,max32-uart";
+			reg = <0x40081400 0x400>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 4>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
+			interrupts = <88 0>;
+			status = "disabled";
+		};
+
+		spi0: spi@400be000 {
+			compatible = "adi,max32-spi";
+			reg = <0x400be000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 16>;
+			interrupts = <56 0>;
+			status = "disabled";
+		};
+
+		spi1: spi@40046000 {
+			compatible = "adi,max32-spi";
+			reg = <0x40046000 0x2000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
+			interrupts = <16 0>;
+			status = "disabled";
+		};
+
+		dma0: dma@40028000 {
+			compatible = "adi,max32-dma";
+			reg = <0x40028000 0x1000>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
+			interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
+			dma-channels = <4>;
+			status = "disabled";
+			#dma-cells = <2>;
+		};
+
+		wdt1: watchdog@40080800  {
+			compatible = "adi,max32-watchdog";
+			reg = <0x40080800 0x400>;
+			interrupts = <57 0>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
+			status = "disabled";
+		};
+
+		lptimer0: timer@40080c00 {
+			compatible = "adi,max32-timer";
+			reg = <0x40080c00 0x400>;
+			interrupts = <9 0>;
+			status = "disabled";
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
+			prescaler = <1>;
+			pwm {
+				compatible = "adi,max32-pwm";
+				status = "disabled";
+				#pwm-cells = <3>;
+			};
+			counter {
+				compatible = "adi,max32-counter";
+				status = "disabled";
+			};
+		};
+
+		lptimer1: timer@40081000 {
+			compatible = "adi,max32-timer";
+			reg = <0x40081000 0x400>;
+			interrupts = <10 0>;
+			status = "disabled";
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 3>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
+			prescaler = <1>;
+			pwm {
+				compatible = "adi,max32-pwm";
+				status = "disabled";
+				#pwm-cells = <3>;
+			};
+			counter {
+				compatible = "adi,max32-counter";
+				status = "disabled";
+			};
+		};
+
+		w1: w1@4003d000 {
+			compatible = "adi,max32-w1";
+			reg = <0x4003d000 0x1000>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 13>;
+			interrupts = <67 0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/soc/adi/max32/CMakeLists.txt b/soc/adi/max32/CMakeLists.txt
index 9761cdcf0b3..41041da7e08 100644
--- a/soc/adi/max32/CMakeLists.txt
+++ b/soc/adi/max32/CMakeLists.txt
@@ -6,5 +6,6 @@ zephyr_include_directories(common)
 zephyr_sources(soc.c)
 
 zephyr_linker_sources_ifdef(CONFIG_SOC_FLASH_MAX32 SECTIONS flash.ld)
+zephyr_linker_sources_ifdef(CONFIG_SOC_MAX78002 SECTIONS max78002.ld)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/adi/max32/Kconfig b/soc/adi/max32/Kconfig
index 8f1b8d9eb2d..b2bdc351518 100644
--- a/soc/adi/max32/Kconfig
+++ b/soc/adi/max32/Kconfig
@@ -37,6 +37,9 @@ config SOC_MAX32680
 config SOC_MAX32690
 	select CPU_CORTEX_M4
 
+config SOC_MAX78002_M4
+	select CPU_CORTEX_M4
+
 if SOC_FAMILY_MAX32
 
 config MAX32_ON_ENTER_CPU_IDLE_HOOK
diff --git a/soc/adi/max32/Kconfig.defconfig b/soc/adi/max32/Kconfig.defconfig
index eb33fc2daa9..5a5fd567fc8 100644
--- a/soc/adi/max32/Kconfig.defconfig
+++ b/soc/adi/max32/Kconfig.defconfig
@@ -5,7 +5,7 @@
 
 if SOC_FAMILY_MAX32
 
-rsource "Kconfig.defconfig.max32*"
+rsource "Kconfig.defconfig.max*"
 
 config SRAM_VECTOR_TABLE
 	default y
diff --git a/soc/adi/max32/Kconfig.defconfig.max78002 b/soc/adi/max32/Kconfig.defconfig.max78002
new file mode 100644
index 00000000000..307a7570888
--- /dev/null
+++ b/soc/adi/max32/Kconfig.defconfig.max78002
@@ -0,0 +1,14 @@
+# Analog Devices MAX78002 MCU
+
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MAX78002
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
+
+config NUM_IRQS
+	default 105
+
+endif # SOC_MAX78002
diff --git a/soc/adi/max32/Kconfig.soc b/soc/adi/max32/Kconfig.soc
index e56456047fb..130d9b88b1f 100644
--- a/soc/adi/max32/Kconfig.soc
+++ b/soc/adi/max32/Kconfig.soc
@@ -57,6 +57,14 @@ config SOC_MAX32690_M4
 	bool
 	select SOC_MAX32690
 
+config SOC_MAX78002
+	bool
+	select SOC_FAMILY_MAX32
+
+config SOC_MAX78002_M4
+	bool
+	select SOC_MAX78002
+
 config SOC
 	default "max32655" if SOC_MAX32655
 	default "max32662" if SOC_MAX32662
@@ -66,3 +74,4 @@ config SOC
 	default "max32675" if SOC_MAX32675
 	default "max32680" if SOC_MAX32680
 	default "max32690" if SOC_MAX32690
+	default "max78002" if SOC_MAX78002
diff --git a/soc/adi/max32/max78002.ld b/soc/adi/max32/max78002.ld
new file mode 100644
index 00000000000..5dd693c0f58
--- /dev/null
+++ b/soc/adi/max32/max78002.ld
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_PROLOGUE(.shared,, SUBALIGN(4))
+{
+	_shared = .;
+	*(.mailbox*)
+	*(.shared*)
+	_eshared = .;
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
diff --git a/soc/adi/max32/soc.yml b/soc/adi/max32/soc.yml
index 701509dc15c..3f164890071 100644
--- a/soc/adi/max32/soc.yml
+++ b/soc/adi/max32/soc.yml
@@ -20,3 +20,6 @@ family:
   - name: max32690
     cpuclusters:
     - name: m4
+  - name: max78002
+    cpuclusters:
+    - name: m4