From f419a6778f05086965341e74b86881fa309cd7a9 Mon Sep 17 00:00:00 2001
From: Sadik Ozer <sadik.ozer@analog.com>
Date: Tue, 6 Aug 2024 10:15:03 +0300
Subject: [PATCH] boards: arm: adi: Enable display for MAX32690EVKIT board

MAX32690EVKIT board has CFAF128128B1-0145T display which
is 128x128 graphic display.
The pins goes to display is not standard SPI interface, it requires
SPI bitbanging to drive display.

This commit enables mpi dbi display support with LVGL graphic library
Pin connection of display is 3wire mode

Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
---
 boards/adi/max32690evkit/Kconfig.defconfig    | 29 ++++++++++++
 .../max32690evkit_max32690_m4.dts             | 46 +++++++++++++++++++
 2 files changed, 75 insertions(+)
 create mode 100644 boards/adi/max32690evkit/Kconfig.defconfig

diff --git a/boards/adi/max32690evkit/Kconfig.defconfig b/boards/adi/max32690evkit/Kconfig.defconfig
new file mode 100644
index 00000000000..342cc0ca513
--- /dev/null
+++ b/boards/adi/max32690evkit/Kconfig.defconfig
@@ -0,0 +1,29 @@
+# MAX32690EVKIT boards configuration
+
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MAX32690EVKIT
+
+if DISPLAY
+
+config MIPI_DBI_SPI_3WIRE
+	default y
+
+if LVGL
+
+config LV_Z_BITS_PER_PIXEL
+	default 16
+
+choice LV_COLOR_DEPTH
+	default LV_COLOR_DEPTH_16  # 16 bit per pixel
+endchoice
+
+config LV_COLOR_16_SWAP
+	default y
+
+endif # LVGL
+
+endif # DISPLAY
+
+endif # BOARD_MAX32690EVKIT
diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts
index 5ba05dac63b..85b9d251e07 100644
--- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts
+++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts
@@ -10,6 +10,7 @@
 #include <adi/max32/max32690-pinctrl.dtsi>
 #include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
 
 / {
 	model = "Analog Devices MAX32690EVKIT";
@@ -20,6 +21,7 @@
 		zephyr,shell-uart = &uart2;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
+		zephyr,display = &st7735;
 	};
 
 	leds {
@@ -49,6 +51,50 @@
 		sw0 = &pb0;
 		watchdog0 = &wdt0;
 	 };
+
+	mipi_dbi {
+		compatible = "zephyr,mipi-dbi-spi";
+		spi-dev = <&spibb0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "okay";
+
+		st7735: st7735@0 {
+			compatible = "sitronix,st7735r";
+			mipi-max-frequency = <DT_FREQ_M(6)>;
+			mipi-mode = <MIPI_DBI_MODE_SPI_3WIRE>;
+
+			reg = <0>;
+			width = <130>;
+			height = <132>;
+			x-offset = <0>;
+			y-offset = <0>;
+			madctl = <0xc0>;
+			colmod = <0x05>;
+			vmctr1 = <0x51>;
+			pwctr1 = [02 02];
+			pwctr2 = [c5];
+			pwctr3 = [0d 00];
+			pwctr4 = [8d 1a];
+			pwctr5 = [8d ee];
+			frmctr1 = [02 35 36];
+			frmctr2 = [02 35 36];
+			frmctr3 = [02 35 36 02 35 36];
+			gamctrp1 = [0a 1c 0c 14 33 2b 24 28 27 25 2c 39 00 05 03 0d];
+			gamctrn1 = [0a 1c 0c 14 33 2b 24 28 27 25 2d 3a 00 05 03 0d];
+		};
+	};
+
+	spibb0: spibb0 {
+		compatible = "zephyr,spi-bitbang";
+		status="okay";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clk-gpios = <&gpio2 25 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>;
+		mosi-gpios = <&gpio2 24 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>;
+		cs-gpios = <&gpio2 11 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>;
+	};
 };
 
 &clk_ipo {