diff --git a/boards/adi/max32690evkit/Kconfig.defconfig b/boards/adi/max32690evkit/Kconfig.defconfig new file mode 100644 index 00000000000..342cc0ca513 --- /dev/null +++ b/boards/adi/max32690evkit/Kconfig.defconfig @@ -0,0 +1,29 @@ +# MAX32690EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAX32690EVKIT + +if DISPLAY + +config MIPI_DBI_SPI_3WIRE + default y + +if LVGL + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 # 16 bit per pixel +endchoice + +config LV_COLOR_16_SWAP + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_MAX32690EVKIT diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts index 5ba05dac63b..85b9d251e07 100644 --- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts @@ -10,6 +10,7 @@ #include #include #include +#include / { model = "Analog Devices MAX32690EVKIT"; @@ -20,6 +21,7 @@ zephyr,shell-uart = &uart2; zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,display = &st7735; }; leds { @@ -49,6 +51,50 @@ sw0 = &pb0; watchdog0 = &wdt0; }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spibb0>; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + st7735: st7735@0 { + compatible = "sitronix,st7735r"; + mipi-max-frequency = ; + mipi-mode = ; + + reg = <0>; + width = <130>; + height = <132>; + x-offset = <0>; + y-offset = <0>; + madctl = <0xc0>; + colmod = <0x05>; + vmctr1 = <0x51>; + pwctr1 = [02 02]; + pwctr2 = [c5]; + pwctr3 = [0d 00]; + pwctr4 = [8d 1a]; + pwctr5 = [8d ee]; + frmctr1 = [02 35 36]; + frmctr2 = [02 35 36]; + frmctr3 = [02 35 36 02 35 36]; + gamctrp1 = [0a 1c 0c 14 33 2b 24 28 27 25 2c 39 00 05 03 0d]; + gamctrn1 = [0a 1c 0c 14 33 2b 24 28 27 25 2d 3a 00 05 03 0d]; + }; + }; + + spibb0: spibb0 { + compatible = "zephyr,spi-bitbang"; + status="okay"; + #address-cells = <1>; + #size-cells = <0>; + clk-gpios = <&gpio2 25 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; + mosi-gpios = <&gpio2 24 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; + cs-gpios = <&gpio2 11 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; + }; }; &clk_ipo {