diff --git a/dts/bindings/clock/nxp,imx-anatop.yaml b/dts/bindings/clock/nxp,imx-anatop.yaml
new file mode 100644
index 00000000000..362968dd4c4
--- /dev/null
+++ b/dts/bindings/clock/nxp,imx-anatop.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX ANATOP (Analog Clock Controller Module) IP node
+
+compatible: "nxp,imx-anatop"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+        required: true
+
+    label:
+        required: true
+
+    "#clock-cells":
+        type: int
+        const: 4
+        required: true
+        description: Number of items to expect in a clock specifier
+
+    "#pll-clock-cells":
+        type: int
+        const: 3
+        required: true
+        description: Number of items to expect in a PLL specifier
+
+clock-cells:
+    - name
+    - offset
+    - bits
+    - value
+
+pll-clock-cells:
+    - offset
+    - bits
+    - value
diff --git a/dts/bindings/i2s/nxp,mcux-i2s.yaml b/dts/bindings/i2s/nxp,mcux-i2s.yaml
new file mode 100644
index 00000000000..c68cd9f41b0
--- /dev/null
+++ b/dts/bindings/i2s/nxp,mcux-i2s.yaml
@@ -0,0 +1,70 @@
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP mcux SAI-I2S controller
+
+compatible: "nxp,mcux-i2s"
+
+include: [i2s-controller.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    dma-names:
+      required: true
+
+    nxp,tx-dma-channel:
+      type: int
+      required: true
+      description: tx dma channel number
+
+    nxp,rx-dma-channel:
+      type: int
+      required: true
+      description: rx dma channel number
+
+    nxp,tx-sync-mode:
+      type: boolean
+      required: false
+      description: tx sync mode
+
+    nxp,rx-sync-mode:
+      type: boolean
+      required: false
+      description: rx sync mode
+
+    pre-div:
+      type: int
+      required: false
+      description: pre divider
+
+    podf:
+      type: int
+      required: false
+      description: post-divider fraction
+
+    pll-clocks:
+      type: phandle-array
+      required: false
+      description: pll settings
+      specifier-space: pll-clock
+
+    pll-clock-names:
+      required: false
+      type: string-array
+      description: Provided names of pll-clock specifiers
+
+    pinmuxes:
+      type: phandle-array
+      required: false
+      specifier-space: pinmux
+      description: iomux settings
+
+    nxp,tx-channel:
+      type: int
+      required: false
+      description: tx channel the maximum number is SOC dependent
diff --git a/dts/bindings/pinctrl/nxp,imx-pinmux.yaml b/dts/bindings/pinctrl/nxp,imx-pinmux.yaml
new file mode 100644
index 00000000000..66c1ed3a0df
--- /dev/null
+++ b/dts/bindings/pinctrl/nxp,imx-pinmux.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2021, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX IOMUXC node
+
+compatible: "nxp,imx-pinmux"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+pinmux-cells:
+  - pin
+  - function
diff --git a/include/dt-bindings/clock/imx_ccm.h b/include/dt-bindings/clock/imx_ccm.h
index 866bc344ca8..17d4b520630 100644
--- a/include/dt-bindings/clock/imx_ccm.h
+++ b/include/dt-bindings/clock/imx_ccm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NXP
+ * Copyright (c) 2017-2021, NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,5 +19,8 @@
 #define IMX_CCM_UART_CLK		9
 #define IMX_CCM_CAN_CLK			10
 #define IMX_CCM_GPT_CLK			11
+#define IMX_CCM_SAI1_CLK		12
+#define IMX_CCM_SAI2_CLK		13
+#define IMX_CCM_SAI3_CLK		14
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */