diff --git a/dts/arm/microchip/mec1701qsz.dtsi b/dts/arm/microchip/mec1701qsz.dtsi new file mode 100644 index 00000000000..e4b2846dbaf --- /dev/null +++ b/dts/arm/microchip/mec1701qsz.dtsi @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2019 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m4f"; + reg = <0>; + }; + }; + + flash0: flash@b0000 { + reg = <0x000B0000 0x68000>; + }; + + sram0: memory@118000 { + compatible = "mmio-sram"; + reg = <0x00118000 0x10000>; + }; + + soc { + uart0: uart@400f2400 { + compatible = "ns16550"; + reg = <0x400f2400 0x400>; + interrupts = <40 0>; + current-speed = <38400>; + label = "UART_0"; + reg-shift = <0>; + }; + uart1: uart@400f2800 { + compatible = "ns16550"; + reg = <0x400f2800 0x400>; + interrupts = <41 0>; + current-speed = <38400>; + label = "UART_1"; + reg-shift = <0>; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/soc/arm/microchip_mec/CMakeLists.txt b/soc/arm/microchip_mec/CMakeLists.txt new file mode 100644 index 00000000000..ac7ce7faba7 --- /dev/null +++ b/soc/arm/microchip_mec/CMakeLists.txt @@ -0,0 +1 @@ +add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/microchip_mec/Kconfig b/soc/arm/microchip_mec/Kconfig new file mode 100644 index 00000000000..163ff06072a --- /dev/null +++ b/soc/arm/microchip_mec/Kconfig @@ -0,0 +1,19 @@ +# Kconfig - Microchip MEC MCU line +# +# Copyright (c) 2018, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# +config SOC_FAMILY_MEC + bool + # omit prompt to signify a "hidden" option + +if SOC_FAMILY_MEC +config SOC_FAMILY + string + default "microchip_mec" + +# Select SoC Part No. and configuration options +source "soc/arm/microchip_mec/*/Kconfig.soc" + +endif # SOC_FAMILY_MEC diff --git a/soc/arm/microchip_mec/Kconfig.defconfig b/soc/arm/microchip_mec/Kconfig.defconfig new file mode 100644 index 00000000000..a987bfcc841 --- /dev/null +++ b/soc/arm/microchip_mec/Kconfig.defconfig @@ -0,0 +1 @@ +source "soc/arm/microchip_mec/*/Kconfig.defconfig.series" diff --git a/soc/arm/microchip_mec/Kconfig.soc b/soc/arm/microchip_mec/Kconfig.soc new file mode 100644 index 00000000000..a8ab0ddcf24 --- /dev/null +++ b/soc/arm/microchip_mec/Kconfig.soc @@ -0,0 +1,8 @@ +# Kconfig.soc - Microchip MEC1701 MCU line +# +# Copyright (c) 2018 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +source "soc/arm/microchip_mec/*/Kconfig.series" diff --git a/soc/arm/microchip_mec/mec1701/CMakeLists.txt b/soc/arm/microchip_mec/mec1701/CMakeLists.txt new file mode 100644 index 00000000000..b304980e28f --- /dev/null +++ b/soc/arm/microchip_mec/mec1701/CMakeLists.txt @@ -0,0 +1,3 @@ +zephyr_sources( + soc.c + ) diff --git a/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.mec1701qsz b/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.mec1701qsz new file mode 100644 index 00000000000..1b86463881b --- /dev/null +++ b/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.mec1701qsz @@ -0,0 +1,25 @@ +# Kconfig - Microchip MEC1701QSZ MCU +# +# Copyright (c) 2018 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_MEC1701_QSZ + +config SOC + string + default "mec1701qsz" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 48000000 + +if SERIAL + +config UART_NS16550 + def_bool y + +endif # SERIAL + +endif # SOC_MEC1701_QSZ diff --git a/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.series b/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.series new file mode 100644 index 00000000000..9c2b1397b57 --- /dev/null +++ b/soc/arm/microchip_mec/mec1701/Kconfig.defconfig.series @@ -0,0 +1,22 @@ +# Kconfig - Microchip MEC MCU series configuration options +# +# Copyright (c) 2018 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_MEC1701X + +config SOC_SERIES + string + default "mec1701" + +config NUM_IRQS + int + # must be >= the highest interrupt number used + # - include the UART interrupts + #for the moment 42 needs to be corrected in terms of devices added + default 42 + +source "soc/arm/microchip_mec/mec1701/Kconfig.defconfig.mec1701*" +endif # SOC_SERIES_MEC1701X diff --git a/soc/arm/microchip_mec/mec1701/Kconfig.series b/soc/arm/microchip_mec/mec1701/Kconfig.series new file mode 100644 index 00000000000..a184d4de6ba --- /dev/null +++ b/soc/arm/microchip_mec/mec1701/Kconfig.series @@ -0,0 +1,17 @@ +# Kconfig - Microchip MEC1701 MCU core series +# +# Copyright (c) 2018 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_MEC1701X + bool "Microchip MEC1701X Series" + select CPU_CORTEX_M + select CPU_CORTEX_M4 + select SOC_FAMILY_MEC + select CPU_HAS_SYSTICK + select SYS_POWER_LOW_POWER_STATE_SUPPORTED + select CPU_HAS_FPU + help + Enable support for Microchip MEC Cortex-M4 MCU series diff --git a/soc/arm/microchip_mec/mec1701/Kconfig.soc b/soc/arm/microchip_mec/mec1701/Kconfig.soc new file mode 100644 index 00000000000..d56b6148215 --- /dev/null +++ b/soc/arm/microchip_mec/mec1701/Kconfig.soc @@ -0,0 +1,17 @@ +# Kconfig - Microchip MEC1701 MCU core series + +# +# Copyright (c) 2018 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +choice +prompt "MEC1701 Selection" +depends on SOC_SERIES_MEC1701X + +config SOC_MEC1701_QSZ + bool "MEC1701_QSZ" + select HAS_MEC_HAL + +endchoice diff --git a/soc/arm/microchip_mec/mec1701/dts_fixup.h b/soc/arm/microchip_mec/mec1701/dts_fixup.h new file mode 100644 index 00000000000..4e428dfdf74 --- /dev/null +++ b/soc/arm/microchip_mec/mec1701/dts_fixup.h @@ -0,0 +1,24 @@ +/* This file is a temporary workaround for mapping of the generated information + * to the current driver definitions. This will be removed when the drivers + * are modified to handle the generated information, or the mapping of + * generated data matches the driver definitions. + */ + + +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define CONFIG_NS16550_REG_SHIFT DT_NS16550_400F2400_REG_SHIFT +#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_400F2400_BASE_ADDRESS +#define DT_UART_NS16550_PORT_0_CLK_FREQ 1843200 +#define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_400F2400_LABEL +#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_400F2400_CURRENT_SPEED +#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_400F2400_IRQ_0 +#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_0_IRQ_0_PRIORITY +#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Deault */ + +#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_400F2800_BASE_ADDRESS +#define DT_UART_NS16550_PORT_1_CLK_FREQ 1843200 +#define CONFIG_UART_NS16550_PORT_1_NAME DT_NS16550_400F2800_LABEL +#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_400F2800_CURRENT_SPEED +#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_400F2800_IRQ_0 +#define CONFIG_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_1_IRQ_0_PRIORITY +#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */ diff --git a/soc/arm/microchip_mec/mec1701/linker.ld b/soc/arm/microchip_mec/mec1701/linker.ld new file mode 100644 index 00000000000..b6ccb02793c --- /dev/null +++ b/soc/arm/microchip_mec/mec1701/linker.ld @@ -0,0 +1,9 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/microchip_mec/mec1701/soc.c b/soc/arm/microchip_mec/mec1701/soc.c new file mode 100644 index 00000000000..83226f5eeaf --- /dev/null +++ b/soc/arm/microchip_mec/mec1701/soc.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2018 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + + +static int soc_init(struct device *dev) +{ + __IO uint32_t *girc_enable_set; + + __enable_irq(); + + /* Enable clocks for Interrupts and CPU */ + PCR_INST->CLK_REQ_1_b.INT_CLK_REQ = 1; + PCR_INST->CLK_REQ_1_b.PROCESSOR_CLK_REQ = 1; + + /* Route all interrupts from EC to NVIC */ + EC_REG_BANK_INST->INTERRUPT_CONTROL = 0x1; + for (girc_enable_set = (uint32_t *)&INTS_INST->GIRQ08_EN_SET; + girc_enable_set <= &INTS_INST->GIRQ15_EN_SET; + girc_enable_set += 5) { + /* This probably will require tunning, but drawing 8.2 also + illustrates how to diasable spurious interrupts */ + *girc_enable_set = 0xFFFFFFFF; + } + + return 0; +} + +SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/arm/microchip_mec/mec1701/soc.h b/soc/arm/microchip_mec/mec1701/soc.h new file mode 100644 index 00000000000..522b9cd86bf --- /dev/null +++ b/soc/arm/microchip_mec/mec1701/soc.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2018 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __MEC_SOC_H +#define __MEC_SOC_H + +#define SYSCLK_DEFAULT_IOSC_HZ MHZ(48) + +#ifndef _ASMLANGUAGE + +#include "MCHP_MEC1701.h" + +#endif + +#endif