arch/x86: refactor kernel_arch_thread.h
This data is subarchitecture-specific, so move it to ia32/ and add a layer of indirection at the architecture level. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse
Anas Nashif
parent
aa6d5b43f2
commit
f40fe36ca6
2 changed files with 233 additions and 220 deletions
230
arch/x86/include/ia32/kernel_arch_thread.h
Normal file
230
arch/x86/include/ia32/kernel_arch_thread.h
Normal file
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@ -0,0 +1,230 @@
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/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Per-arch thread definition
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*
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* This file contains definitions for
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*
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* struct _thread_arch
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* struct _callee_saved
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*
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* necessary to instantiate instances of struct k_thread.
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*/
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#ifndef ZEPHYR_ARCH_X86_INCLUDE_IA32_KERNEL_ARCH_THREAD_H_
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#define ZEPHYR_ARCH_X86_INCLUDE_IA32_KERNEL_ARCH_THREAD_H_
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/**
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* Floating point register set alignment.
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*
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* If support for SSEx extensions is enabled a 16 byte boundary is required,
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* since the 'fxsave' and 'fxrstor' instructions require this. In all other
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* cases a 4 byte boundary is sufficient.
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*/
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#ifdef CONFIG_SSE
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#define FP_REG_SET_ALIGN 16
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#else
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#define FP_REG_SET_ALIGN 4
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#endif
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#ifndef _ASMLANGUAGE
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#include <stdint.h>
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/*
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* The following structure defines the set of 'non-volatile' integer registers.
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* These registers must be preserved by a called C function. These are the
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* only registers that need to be saved/restored when a cooperative context
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* switch occurs.
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*/
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struct _callee_saved {
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unsigned long esp;
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/*
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* The following registers are considered non-volatile, i.e.
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* callee-save,
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* but their values are pushed onto the stack rather than stored in the
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* TCS
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* structure:
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*
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* unsigned long ebp;
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* unsigned long ebx;
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* unsigned long esi;
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* unsigned long edi;
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*/
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};
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typedef struct _callee_saved _callee_saved_t;
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/*
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* The macros CONFIG_{LAZY|EAGER}_FP_SHARING shall be set to indicate that the
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* saving/restoring of the traditional x87 floating point (and MMX) registers
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* are supported by the kernel's context swapping code. The macro
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* CONFIG_SSE shall _also_ be set if saving/restoring of the XMM
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* registers is also supported in the kernel's context swapping code.
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*/
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#if defined(CONFIG_EAGER_FP_SHARING) || defined(CONFIG_LAZY_FP_SHARING)
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/* definition of a single x87 (floating point / MMX) register */
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typedef struct s_FpReg {
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unsigned char reg[10]; /* 80 bits: ST[0-7] */
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} tFpReg;
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/*
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* The following is the "normal" floating point register save area, or
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* more accurately the save area required by the 'fnsave' and 'frstor'
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* instructions. The structure matches the layout described in the
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* "Intel(r) 64 and IA-32 Architectures Software Developer's Manual
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* Volume 1: Basic Architecture": Protected Mode x87 FPU State Image in
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* Memory, 32-Bit Format.
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*/
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typedef struct s_FpRegSet { /* # of bytes: name of register */
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unsigned short fcw; /* 2 : x87 FPU control word */
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unsigned short pad1; /* 2 : N/A */
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unsigned short fsw; /* 2 : x87 FPU status word */
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unsigned short pad2; /* 2 : N/A */
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unsigned short ftw; /* 2 : x87 FPU tag word */
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unsigned short pad3; /* 2 : N/A */
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unsigned int fpuip; /* 4 : x87 FPU instruction pointer offset */
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unsigned short cs; /* 2 : x87 FPU instruction pointer selector */
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unsigned short fop : 11; /* 2 : x87 FPU opcode */
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unsigned short pad4 : 5; /* : 5 bits = 00000 */
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unsigned int fpudp; /* 4 : x87 FPU instr operand ptr offset */
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unsigned short ds; /* 2 : x87 FPU instr operand ptr selector */
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unsigned short pad5; /* 2 : N/A */
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tFpReg fpReg[8]; /* 80 : ST0 -> ST7 */
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} tFpRegSet __aligned(FP_REG_SET_ALIGN);
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#ifdef CONFIG_SSE
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/* definition of a single x87 (floating point / MMX) register */
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typedef struct s_FpRegEx {
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unsigned char reg[10]; /* 80 bits: ST[0-7] or MM[0-7] */
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unsigned char rsrvd[6]; /* 48 bits: reserved */
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} tFpRegEx;
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/* definition of a single XMM register */
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typedef struct s_XmmReg {
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unsigned char reg[16]; /* 128 bits: XMM[0-7] */
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} tXmmReg;
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/*
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* The following is the "extended" floating point register save area, or
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* more accurately the save area required by the 'fxsave' and 'fxrstor'
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* instructions. The structure matches the layout described in the
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* "Intel 64 and IA-32 Architectures Software Developer's Manual
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* Volume 2A: Instruction Set Reference, A-M", except for the bytes from offset
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* 464 to 511 since these "are available to software use. The processor does
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* not write to bytes 464:511 of an FXSAVE area".
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*
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* This structure must be aligned on a 16 byte boundary when the instructions
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* fxsave/fxrstor are used to write/read the data to/from the structure.
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*/
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typedef struct s_FpRegSetEx /* # of bytes: name of register */
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{
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unsigned short fcw; /* 2 : x87 FPU control word */
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unsigned short fsw; /* 2 : x87 FPU status word */
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unsigned char ftw; /* 1 : x87 FPU abridged tag word */
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unsigned char rsrvd0; /* 1 : reserved */
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unsigned short fop; /* 2 : x87 FPU opcode */
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unsigned int fpuip; /* 4 : x87 FPU instruction pointer offset */
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unsigned short cs; /* 2 : x87 FPU instruction pointer selector */
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unsigned short rsrvd1; /* 2 : reserved */
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unsigned int fpudp; /* 4 : x87 FPU instr operand ptr offset */
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unsigned short ds; /* 2 : x87 FPU instr operand ptr selector */
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unsigned short rsrvd2; /* 2 : reserved */
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unsigned int mxcsr; /* 4 : MXCSR register state */
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unsigned int mxcsrMask; /* 4 : MXCSR register mask */
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tFpRegEx fpReg[8]; /* 128 : x87 FPU/MMX registers */
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tXmmReg xmmReg[8]; /* 128 : XMM registers */
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unsigned char rsrvd3[176]; /* 176 : reserved */
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} tFpRegSetEx __aligned(FP_REG_SET_ALIGN);
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#else /* CONFIG_SSE == 0 */
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typedef struct s_FpRegSetEx {
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} tFpRegSetEx;
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#endif /* CONFIG_SSE == 0 */
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#else /* !CONFIG_LAZY_FP_SHARING && !CONFIG_EAGER_FP_SHARING */
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/* empty floating point register definition */
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typedef struct s_FpRegSet {
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} tFpRegSet;
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typedef struct s_FpRegSetEx {
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} tFpRegSetEx;
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#endif /* CONFIG_LAZY_FP_SHARING || CONFIG_EAGER_FP_SHARING */
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/*
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* The following structure defines the set of 'volatile' x87 FPU/MMX/SSE
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* registers. These registers need not be preserved by a called C function.
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* Given that they are not preserved across function calls, they must be
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* save/restored (along with s_coopFloatReg) when a preemptive context
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* switch occurs.
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*/
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typedef struct s_preempFloatReg {
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union {
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/* threads with K_FP_REGS utilize this format */
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tFpRegSet fpRegs;
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/* threads with K_SSE_REGS utilize this format */
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tFpRegSetEx fpRegsEx;
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} floatRegsUnion;
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} tPreempFloatReg;
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/*
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* The thread control structure definition. It contains the
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* various fields to manage a _single_ thread. The TCS will be aligned
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* to the appropriate architecture specific boundary via the
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* z_new_thread() call.
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*/
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struct _thread_arch {
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#if defined(CONFIG_LAZY_FP_SHARING)
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/*
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* Nested exception count to maintain setting of EXC_ACTIVE flag across
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* outermost exception. EXC_ACTIVE is used by z_swap() lazy FP
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* save/restore and by debug tools.
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*/
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unsigned excNestCount; /* nested exception count */
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#endif /* CONFIG_LAZY_FP_SHARING */
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/*
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* The location of all floating point related structures/fields MUST be
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* located at the end of struct k_thread. This way only the
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* threads that actually utilize non-integer capabilities need to
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* account for the increased memory required for storing FP state when
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* sizing stacks.
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*
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* Given that stacks "grow down" on IA-32, and the TCS is located
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* at the start of a thread's "workspace" memory, the stacks of
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* threads that do not utilize floating point instruction can
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* effectively consume the memory occupied by the 'tPreempFloatReg'
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* struct without ill effect.
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*/
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tPreempFloatReg preempFloatReg; /* volatile float register storage */
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};
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typedef struct _thread_arch _thread_arch_t;
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_ARCH_X86_INCLUDE_IA32_KERNEL_ARCH_THREAD_H_ */
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@ -1,230 +1,13 @@
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/*
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* Copyright (c) 2017 Intel Corporation
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*
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* Copyright (c) 2019 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Per-arch thread definition
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*
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* This file contains definitions for
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*
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* struct _thread_arch
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* struct _callee_saved
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*
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* necessary to instantiate instances of struct k_thread.
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*/
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#ifndef ZEPHYR_ARCH_X86_INCLUDE_KERNEL_ARCH_THREAD_H_
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#define ZEPHYR_ARCH_X86_INCLUDE_KERNEL_ARCH_THREAD_H_
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/**
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* Floating point register set alignment.
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*
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* If support for SSEx extensions is enabled a 16 byte boundary is required,
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* since the 'fxsave' and 'fxrstor' instructions require this. In all other
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* cases a 4 byte boundary is sufficient.
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*/
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#ifdef CONFIG_SSE
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#define FP_REG_SET_ALIGN 16
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#else
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#define FP_REG_SET_ALIGN 4
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#ifndef CONFIG_X86_LONGMODE
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#include <ia32/kernel_arch_thread.h>
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#endif
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#ifndef _ASMLANGUAGE
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#include <stdint.h>
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/*
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* The following structure defines the set of 'non-volatile' integer registers.
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* These registers must be preserved by a called C function. These are the
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* only registers that need to be saved/restored when a cooperative context
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* switch occurs.
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*/
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struct _callee_saved {
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unsigned long esp;
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/*
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* The following registers are considered non-volatile, i.e.
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* callee-save,
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* but their values are pushed onto the stack rather than stored in the
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* TCS
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* structure:
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*
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* unsigned long ebp;
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* unsigned long ebx;
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* unsigned long esi;
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* unsigned long edi;
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*/
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};
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typedef struct _callee_saved _callee_saved_t;
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/*
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* The macros CONFIG_{LAZY|EAGER}_FP_SHARING shall be set to indicate that the
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* saving/restoring of the traditional x87 floating point (and MMX) registers
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* are supported by the kernel's context swapping code. The macro
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* CONFIG_SSE shall _also_ be set if saving/restoring of the XMM
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* registers is also supported in the kernel's context swapping code.
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*/
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#if defined(CONFIG_EAGER_FP_SHARING) || defined(CONFIG_LAZY_FP_SHARING)
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/* definition of a single x87 (floating point / MMX) register */
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typedef struct s_FpReg {
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unsigned char reg[10]; /* 80 bits: ST[0-7] */
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} tFpReg;
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/*
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* The following is the "normal" floating point register save area, or
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* more accurately the save area required by the 'fnsave' and 'frstor'
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* instructions. The structure matches the layout described in the
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* "Intel(r) 64 and IA-32 Architectures Software Developer's Manual
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* Volume 1: Basic Architecture": Protected Mode x87 FPU State Image in
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* Memory, 32-Bit Format.
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*/
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typedef struct s_FpRegSet { /* # of bytes: name of register */
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unsigned short fcw; /* 2 : x87 FPU control word */
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unsigned short pad1; /* 2 : N/A */
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unsigned short fsw; /* 2 : x87 FPU status word */
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unsigned short pad2; /* 2 : N/A */
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unsigned short ftw; /* 2 : x87 FPU tag word */
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unsigned short pad3; /* 2 : N/A */
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unsigned int fpuip; /* 4 : x87 FPU instruction pointer offset */
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unsigned short cs; /* 2 : x87 FPU instruction pointer selector */
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unsigned short fop : 11; /* 2 : x87 FPU opcode */
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unsigned short pad4 : 5; /* : 5 bits = 00000 */
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unsigned int fpudp; /* 4 : x87 FPU instr operand ptr offset */
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unsigned short ds; /* 2 : x87 FPU instr operand ptr selector */
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unsigned short pad5; /* 2 : N/A */
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tFpReg fpReg[8]; /* 80 : ST0 -> ST7 */
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} tFpRegSet __aligned(FP_REG_SET_ALIGN);
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#ifdef CONFIG_SSE
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/* definition of a single x87 (floating point / MMX) register */
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typedef struct s_FpRegEx {
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unsigned char reg[10]; /* 80 bits: ST[0-7] or MM[0-7] */
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unsigned char rsrvd[6]; /* 48 bits: reserved */
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} tFpRegEx;
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/* definition of a single XMM register */
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typedef struct s_XmmReg {
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unsigned char reg[16]; /* 128 bits: XMM[0-7] */
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} tXmmReg;
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/*
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* The following is the "extended" floating point register save area, or
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* more accurately the save area required by the 'fxsave' and 'fxrstor'
|
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* instructions. The structure matches the layout described in the
|
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* "Intel 64 and IA-32 Architectures Software Developer's Manual
|
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* Volume 2A: Instruction Set Reference, A-M", except for the bytes from offset
|
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* 464 to 511 since these "are available to software use. The processor does
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* not write to bytes 464:511 of an FXSAVE area".
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*
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* This structure must be aligned on a 16 byte boundary when the instructions
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* fxsave/fxrstor are used to write/read the data to/from the structure.
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*/
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typedef struct s_FpRegSetEx /* # of bytes: name of register */
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{
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unsigned short fcw; /* 2 : x87 FPU control word */
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unsigned short fsw; /* 2 : x87 FPU status word */
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unsigned char ftw; /* 1 : x87 FPU abridged tag word */
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unsigned char rsrvd0; /* 1 : reserved */
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unsigned short fop; /* 2 : x87 FPU opcode */
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unsigned int fpuip; /* 4 : x87 FPU instruction pointer offset */
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unsigned short cs; /* 2 : x87 FPU instruction pointer selector */
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unsigned short rsrvd1; /* 2 : reserved */
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unsigned int fpudp; /* 4 : x87 FPU instr operand ptr offset */
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unsigned short ds; /* 2 : x87 FPU instr operand ptr selector */
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unsigned short rsrvd2; /* 2 : reserved */
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unsigned int mxcsr; /* 4 : MXCSR register state */
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unsigned int mxcsrMask; /* 4 : MXCSR register mask */
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tFpRegEx fpReg[8]; /* 128 : x87 FPU/MMX registers */
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tXmmReg xmmReg[8]; /* 128 : XMM registers */
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unsigned char rsrvd3[176]; /* 176 : reserved */
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} tFpRegSetEx __aligned(FP_REG_SET_ALIGN);
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#else /* CONFIG_SSE == 0 */
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typedef struct s_FpRegSetEx {
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} tFpRegSetEx;
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#endif /* CONFIG_SSE == 0 */
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#else /* !CONFIG_LAZY_FP_SHARING && !CONFIG_EAGER_FP_SHARING */
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/* empty floating point register definition */
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typedef struct s_FpRegSet {
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} tFpRegSet;
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typedef struct s_FpRegSetEx {
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} tFpRegSetEx;
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#endif /* CONFIG_LAZY_FP_SHARING || CONFIG_EAGER_FP_SHARING */
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/*
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* The following structure defines the set of 'volatile' x87 FPU/MMX/SSE
|
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* registers. These registers need not be preserved by a called C function.
|
||||
* Given that they are not preserved across function calls, they must be
|
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* save/restored (along with s_coopFloatReg) when a preemptive context
|
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* switch occurs.
|
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*/
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typedef struct s_preempFloatReg {
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union {
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/* threads with K_FP_REGS utilize this format */
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tFpRegSet fpRegs;
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/* threads with K_SSE_REGS utilize this format */
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tFpRegSetEx fpRegsEx;
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} floatRegsUnion;
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} tPreempFloatReg;
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/*
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* The thread control structure definition. It contains the
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* various fields to manage a _single_ thread. The TCS will be aligned
|
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* to the appropriate architecture specific boundary via the
|
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* z_new_thread() call.
|
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*/
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struct _thread_arch {
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#if defined(CONFIG_LAZY_FP_SHARING)
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/*
|
||||
* Nested exception count to maintain setting of EXC_ACTIVE flag across
|
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* outermost exception. EXC_ACTIVE is used by z_swap() lazy FP
|
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* save/restore and by debug tools.
|
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*/
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unsigned excNestCount; /* nested exception count */
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#endif /* CONFIG_LAZY_FP_SHARING */
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/*
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* The location of all floating point related structures/fields MUST be
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* located at the end of struct k_thread. This way only the
|
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* threads that actually utilize non-integer capabilities need to
|
||||
* account for the increased memory required for storing FP state when
|
||||
* sizing stacks.
|
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*
|
||||
* Given that stacks "grow down" on IA-32, and the TCS is located
|
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* at the start of a thread's "workspace" memory, the stacks of
|
||||
* threads that do not utilize floating point instruction can
|
||||
* effectively consume the memory occupied by the 'tPreempFloatReg'
|
||||
* struct without ill effect.
|
||||
*/
|
||||
tPreempFloatReg preempFloatReg; /* volatile float register storage */
|
||||
};
|
||||
|
||||
typedef struct _thread_arch _thread_arch_t;
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* ZEPHYR_ARCH_X86_INCLUDE_KERNEL_ARCH_THREAD_H_ */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue