soc: riscv: esp32c3: apply CONFIG_RISCV_GP option

esp32c3 has already supported RISC-V GP, just apply new kconfig option
to it. Forcely select CONFIG_RISCV_GP in esp32c3 at first because it
seems to be necessary in the esp32c3 SoC.

Signed-off-by: Jim Shu <cwshu@andestech.com>

soc/riscv/esp32c3/Kconfig.soc

@@ -4,6 +4,7 @@
 config SOC_ESP32C3
 	bool "ESP32C3"
 	select RISCV
+	select RISCV_GP
 	select DYNAMIC_INTERRUPTS
 
 config IDF_TARGET_ESP32C3

soc/riscv/esp32c3/linker.ld

@@ -154,7 +154,9 @@ SECTIONS
     *(.data.*)
     *(.gnu.linkonce.d.*)
     *(.data1)
+#ifdef CONFIG_RISCV_GP
     __global_pointer$ = . + 0x800;
+#endif /* CONFIG_RISCV_GP */
     *(.sdata)
     *(.sdata.*)
     *(.gnu.linkonce.s.*)

soc/riscv/esp32c3/soc.c

@@ -36,6 +36,7 @@ void __attribute__((section(".iram1"))) __start(void)
 	volatile uint32_t *wdt_rtc_protect = (uint32_t *)RTC_CNTL_WDTWPROTECT_REG;
 	volatile uint32_t *wdt_rtc_reg = (uint32_t *)RTC_CNTL_WDTCONFIG0_REG;
 
+#ifdef CONFIG_RISCV_GP
 	/* Configure the global pointer register
 	 * (This should be the first thing startup does, as any other piece of code could be
 	 * relaxed by the linker to access something relative to __global_pointer$)
@@ -44,6 +45,7 @@ void __attribute__((section(".iram1"))) __start(void)
 						".option norelax\n"
 						"la gp, __global_pointer$\n"
 						".option pop");
+#endif /* CONFIG_RISCV_GP */
 
 	__asm__ __volatile__("la t0, _esp32c3_vector_table\n"
 						"csrw mtvec, t0\n");