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tests: drivers: stm32 clock control testing on stm32g0

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target is stm32g0 with pll 64MHz from hsi clock config
target is stm32g0 with pll 64MHz from hse clock config
target is stm32g0 with hsi clock config (no pll)

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2022-02-24 13:05:24 +01:00 • committed by Maureen Helm
commit f3a1d03b5c
8 changed files with 236 additions and 0 deletions
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9
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/CMakeLists.txt Normal file
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# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(stm32_clock_configuration_common)
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})

44
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/clear_clocks.overlay Normal file
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/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay clears clocks back to a state equivalent to what could
* be found in stm32xx.dtsi
*/
&clk_hse {
status = "disabled";
/delete-property/ hse-bypass;
/delete-property/ clock-frequency;
};
&clk_hsi {
status = "disabled";
/delete-property/ hsi-div;
};
&clk_lse {
status = "disabled";
};
&clk_lsi {
status = "disabled";
};
&pll {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
/delete-property/ clocks;
/delete-property/ clock-frequency;
};

19
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/hsi_16.overlay Normal file
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/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi { /* HSI RC: 16MHz, hsi_clk = 16MHz */
status = "okay";
};
&rcc {
clocks = <&clk_hsi>;
clock-frequency = <DT_FREQ_M(16)>;
};

31
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_64_hse_8.overlay Normal file
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/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <16>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(64)>;
};

29
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_64_hsi_16.overlay Normal file
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/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <8>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(64)>;
};

1
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/prj.conf Normal file
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CONFIG_ZTEST=y

90
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/src/test_stm32_clock_configuration.c Normal file
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/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <ztest.h>
#include <soc.h>
#include <drivers/clock_control.h>
#include <drivers/clock_control/stm32_clock_control.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(test);
static void test_sysclk_freq(void)
{
uint32_t soc_sys_clk_freq;
soc_sys_clk_freq = HAL_RCC_GetSysClockFreq();
zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq,
"Expected sysclockfreq: %d. Actual sysclockfreq: %d",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq);
}
static void test_sysclk_src(void)
{
int sys_clk_src = __HAL_RCC_GET_SYSCLK_SOURCE();
#if STM32_SYSCLK_SRC_PLL
zassert_equal(RCC_SYSCLKSOURCE_STATUS_PLLCLK, sys_clk_src,
"Expected sysclk src: PLL. Actual sysclk src: %d",
sys_clk_src);
#elif STM32_SYSCLK_SRC_HSE
zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSE, sys_clk_src,
"Expected sysclk src: HSE. Actual sysclk src: %d",
sys_clk_src);
#elif STM32_SYSCLK_SRC_HSI
zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSI, sys_clk_src,
"Expected sysclk src: HSI. Actual sysclk src: %d",
sys_clk_src);
#elif STM32_SYSCLK_SRC_MSI
zassert_equal(RCC_SYSCLKSOURCE_STATUS_MSI, sys_clk_src,
"Expected sysclk src: MSI. Actual sysclk src: %d",
sys_clk_src);
#else
/* Case not expected */
zassert_true((STM32_SYSCLK_SRC_PLL ||
STM32_SYSCLK_SRC_HSE ||
STM32_SYSCLK_SRC_HSI ||
STM32_SYSCLK_SRC_MSI),
"Not expected. sys_clk_src: %d\n", sys_clk_src);
#endif
}
static void test_pll_src(void)
{
uint32_t pll_src = __HAL_RCC_GET_PLL_OSCSOURCE();
#if STM32_PLL_SRC_HSE
zassert_equal(RCC_PLLSOURCE_HSE, pll_src,
"Expected PLL src: HSE (%d). Actual PLL src: %d",
RCC_PLLSOURCE_HSE, pll_src);
#elif STM32_PLL_SRC_HSI
zassert_equal(RCC_PLLSOURCE_HSI, pll_src,
"Expected PLL src: HSI (%d). Actual PLL src: %d",
RCC_PLLSOURCE_HSI, pll_src);
#elif STM32_PLL_SRC_MSI
zassert_equal(RCC_PLLSOURCE_MSI, pll_src,
"Expected PLL src: MSI (%d). Actual PLL src: %d",
RCC_PLLSOURCE_MSI, pll_src);
#else
zassert_equal(RCC_PLLSOURCE_NONE, pll_src,
"Expected PLL src: none (%d). Actual PLL src: %d",
RCC_PLLSOURCE_NONE, pll_src);
#endif
}
void test_main(void)
{
printk("testing clock config on %s\n", CONFIG_BOARD);
ztest_test_suite(test_stm32_syclck_config,
ztest_unit_test(test_sysclk_freq),
ztest_unit_test(test_sysclk_src),
ztest_unit_test(test_pll_src)
);
ztest_run_test_suite(test_stm32_syclck_config);
}

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tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml Normal file
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common:
timeout: 5
platform_exclude: nucleo_h723zg b_u585i_iot02a
tests:
drivers.stm32_clock_configuration.common.sysclksrc_pll_64_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_64_hse_8.overlay"
platform_allow: nucleo_g071rb
drivers.stm32_clock_configuration.common.sysclksrc_pll_64_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_64_hsi_16.overlay"
platform_allow: nucleo_g071rb
drivers.stm32_clock_configuration.common.sysclksrc_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_g071rb