diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
index 5a22e712e1b..2d81d85343d 100644
--- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
@@ -194,11 +194,7 @@
 
 /* window 3 */
 #define SRAM_TRACE_BASE		(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#if CONFIG_TRACE
 #define SRAM_TRACE_SIZE		0x2000
-#else
-#define SRAM_TRACE_SIZE		0x0
-#endif
 
 #define HP_SRAM_WIN3_BASE       SRAM_TRACE_BASE
 #define HP_SRAM_WIN3_SIZE       SRAM_TRACE_SIZE
diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
index d2e01928480..203e0cc709e 100644
--- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
+++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
@@ -195,11 +195,7 @@
 
 /* window 3 */
 #define SRAM_TRACE_BASE		(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
-#if CONFIG_TRACE
 #define SRAM_TRACE_SIZE		0x2000
-#else
-#define SRAM_TRACE_SIZE		0x0
-#endif
 
 #define HP_SRAM_WIN3_BASE	SRAM_TRACE_BASE
 #define HP_SRAM_WIN3_SIZE	SRAM_TRACE_SIZE