drivers/adc: Add support for Microchip's XEC ADC device
Such ADC is found on mec1501. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com> Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Anas Nashif
parent
bce525fdcf
commit
f3361f4027
5 changed files with 333 additions and 0 deletions
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@ -10,4 +10,5 @@ zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_ADC adc_nrfx_adc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_SAADC adc_nrfx_saadc.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_SAM0 adc_sam0.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_STM32 adc_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_ADC_XEC adc_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE adc_handlers.c)
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@ -64,4 +64,6 @@ source "drivers/adc/Kconfig.sam0"
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source "drivers/adc/Kconfig.stm32"
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source "drivers/adc/Kconfig.xec"
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endif # ADC
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13
drivers/adc/Kconfig.xec
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13
drivers/adc/Kconfig.xec
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@ -0,0 +1,13 @@
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# Kconfig - Microchip XEC ADC configuration
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#
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# Copyright (c) 2019 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config ADC_XEC
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bool "Microchip XEC series ADC driver"
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depends on SOC_FAMILY_MEC
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default y
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help
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Enable ADC driver for Microchip XEC MCU series.
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310
drivers/adc/adc_mchp_xec.c
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310
drivers/adc/adc_mchp_xec.c
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@ -0,0 +1,310 @@
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/*
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* Copyright (c) 2019 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(adc_mchp_xec);
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#include <drivers/adc.h>
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#include <soc.h>
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#include <errno.h>
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#include <assert.h>
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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#define XEC_ADC_VREF_ANALOG 3300
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/* ADC Control Register */
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#define XEC_ADC_CTRL_SINGLE_DONE_STATUS BIT(7)
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#define XEC_ADC_CTRL_REPEAT_DONE_STATUS BIT(6)
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#define XER_ADC_CTRL_SOFT_RESET BIT(4)
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#define XEC_ADC_CTRL_POWER_SAVER_DIS BIT(3)
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#define XEC_ADC_CTRL_START_REPEAT BIT(2)
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#define XEC_ADC_CTRL_START_SINGLE BIT(1)
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#define XEC_ADC_CTRL_ACTIVATE BIT(0)
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struct adc_xec_data {
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struct adc_context ctx;
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u16_t *buffer;
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u16_t *repeat_buffer;
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};
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struct adc_xec_regs {
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u32_t control_reg;
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u32_t delay_reg;
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u32_t status_reg;
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u32_t single_reg;
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u32_t repeat_reg;
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u32_t channel_read_reg[8];
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u32_t unused[18];
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u32_t config_reg;
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u32_t vref_channel_reg;
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u32_t vref_control_reg;
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u32_t sar_control_reg;
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};
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#define ADC_XEC_REG_BASE \
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((struct adc_xec_regs *)(DT_INST_0_MICROCHIP_XEC_ADC_BASE_ADDRESS))
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DEVICE_DECLARE(adc_xec);
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct adc_xec_data *data = CONTAINER_OF(ctx, struct adc_xec_data, ctx);
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struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE;
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data->repeat_buffer = data->buffer;
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adc_regs->single_reg = ctx->sequence.channels;
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adc_regs->control_reg |= XEC_ADC_CTRL_START_SINGLE;
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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bool repeat_sampling)
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{
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struct adc_xec_data *data = CONTAINER_OF(ctx, struct adc_xec_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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static int adc_xec_channel_setup(struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE;
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u32_t reg;
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ARG_UNUSED(dev);
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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return -EINVAL;
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}
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if (channel_cfg->channel_id >= MCHP_ADC_MAX_CHAN) {
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return -EINVAL;
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}
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if (channel_cfg->gain != ADC_GAIN_1) {
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return -EINVAL;
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}
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/* Setup VREF */
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reg = adc_regs->vref_channel_reg;
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reg &= ~MCHP_ADC_CH_VREF_SEL_MASK(channel_cfg->channel_id);
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if (channel_cfg->reference == ADC_REF_INTERNAL) {
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reg |= MCHP_ADC_CH_VREF_SEL_PAD(channel_cfg->channel_id);
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} else if (channel_cfg->reference == ADC_REF_EXTERNAL0) {
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reg |= MCHP_ADC_CH_VREF_SEL_GPIO(channel_cfg->channel_id);
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} else {
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return -EINVAL;
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}
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adc_regs->vref_channel_reg = reg;
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/* Differential mode? */
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reg = adc_regs->sar_control_reg;
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reg &= ~BIT(MCHP_ADC_SAR_CTRL_SELDIFF_POS);
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if (channel_cfg->differential != 0) {
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reg |= MCHP_ADC_SAR_CTRL_SELDIFF_EN;
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}
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adc_regs->sar_control_reg = reg;
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return 0;
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}
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static bool adc_xec_validate_buffer_size(const struct adc_sequence *sequence)
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{
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int chan_count = 0;
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size_t buff_need;
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u32_t chan_mask;
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for (chan_mask = 0x80; chan_mask != 0; chan_mask >>= 1) {
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if (chan_mask & sequence->channels) {
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chan_count++;
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}
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}
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buff_need = chan_count * sizeof(u16_t);
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if (sequence->options) {
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buff_need *= 1 + sequence->options->extra_samplings;
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}
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if (buff_need > sequence->buffer_size) {
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return false;
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}
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return true;
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}
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static int adc_xec_start_read(struct device *dev,
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const struct adc_sequence *sequence)
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{
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struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE;
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struct adc_xec_data *data = dev->driver_data;
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u32_t reg;
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if (sequence->channels & ~MCHP_ADC_MAX_CHAN_MASK) {
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return -EINVAL;
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}
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if (sequence->channels == 0UL) {
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return -EINVAL;
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}
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if (!adc_xec_validate_buffer_size(sequence)) {
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return -ENOMEM;
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}
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/* Setup ADC resolution */
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reg = adc_regs->sar_control_reg;
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reg &= ~MCHP_ADC_SAR_CTRL_RES_MASK;
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if (sequence->resolution == 12) {
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reg |= MCHP_ADC_SAR_CTRL_RES_12_BITS;
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} else if (sequence->resolution == 10) {
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reg |= MCHP_ADC_SAR_CTRL_RES_10_BITS;
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} else {
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return -EINVAL;
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}
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adc_regs->sar_control_reg = reg;
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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return adc_context_wait_for_completion(&data->ctx);
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}
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static int adc_xec_read(struct device *dev,
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const struct adc_sequence *sequence)
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{
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struct adc_xec_data *data = dev->driver_data;
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int error;
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adc_context_lock(&data->ctx, false, NULL);
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error = adc_xec_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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#if defined(CONFIG_ADC_ASYNC)
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static int adc_xec_read_async(struct device *dev,
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const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct adc_xec_data *data = dev->driver_data;
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int error;
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adc_context_lock(&data->ctx, true, async);
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error = adc_xec_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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#endif /* CONFIG_ADC_ASYNC */
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static void xec_adc_get_sample(struct device *dev)
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{
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struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE;
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struct adc_xec_data *data = dev->driver_data;
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u32_t idx;
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u32_t channels = adc_regs->status_reg;
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u32_t ch_status = channels;
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u32_t bit;
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/*
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* Using the enabled channel bit set, from
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* lowest channel number to highest, find out
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* which channel is enabled and copy the ADC
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* values from hardware registers to the data
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* buffer.
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*/
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bit = find_lsb_set(channels);
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while (bit != 0) {
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idx = bit - 1;
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*data->buffer = (u16_t)adc_regs->channel_read_reg[idx];
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data->buffer++;
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channels &= ~BIT(idx);
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bit = find_lsb_set(channels);
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}
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/* Clear the status register */
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adc_regs->status_reg = ch_status;
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}
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static void adc_xec_isr(struct device *dev)
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{
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struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE;
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struct adc_xec_data *data = dev->driver_data;
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u32_t reg;
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/* Clear START_SINGLE bit and clear SINGLE_DONE_STATUS */
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reg = adc_regs->control_reg;
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reg &= ~XEC_ADC_CTRL_START_SINGLE;
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reg |= XEC_ADC_CTRL_SINGLE_DONE_STATUS;
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adc_regs->control_reg = reg;
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/* Also clear GIRQ source status bit */
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MCHP_GIRQ_SRC(MCHP_ADC_GIRQ) = MCHP_ADC_SNG_DONE_GIRQ_VAL;
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xec_adc_get_sample(dev);
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adc_context_on_sampling_done(&data->ctx, dev);
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LOG_DBG("ADC ISR triggered.");
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}
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struct adc_driver_api adc_xec_api = {
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.channel_setup = adc_xec_channel_setup,
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.read = adc_xec_read,
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#if defined(CONFIG_ADC_ASYNC)
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.read_async = adc_xec_read_async,
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#endif
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.ref_internal = XEC_ADC_VREF_ANALOG,
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};
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static int adc_xec_init(struct device *dev)
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{
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struct adc_xec_regs *adc_regs = ADC_XEC_REG_BASE;
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struct adc_xec_data *data = dev->driver_data;
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adc_regs->control_reg = XEC_ADC_CTRL_ACTIVATE
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| XEC_ADC_CTRL_POWER_SAVER_DIS
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| XEC_ADC_CTRL_SINGLE_DONE_STATUS
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| XEC_ADC_CTRL_REPEAT_DONE_STATUS;
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MCHP_GIRQ_SRC(MCHP_ADC_GIRQ) = MCHP_ADC_SNG_DONE_GIRQ_VAL;
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MCHP_GIRQ_ENSET(MCHP_ADC_GIRQ) = MCHP_ADC_SNG_DONE_GIRQ_VAL;
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IRQ_CONNECT(DT_INST_0_MICROCHIP_XEC_ADC_IRQ_0,
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DT_INST_0_MICROCHIP_XEC_ADC_IRQ_0_PRIORITY,
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adc_xec_isr, DEVICE_GET(adc_xec), 0);
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irq_enable(DT_INST_0_MICROCHIP_XEC_ADC_IRQ_0);
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static struct adc_xec_data adc_xec_dev_data_0 = {
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ADC_CONTEXT_INIT_TIMER(adc_xec_dev_data_0, ctx),
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ADC_CONTEXT_INIT_LOCK(adc_xec_dev_data_0, ctx),
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ADC_CONTEXT_INIT_SYNC(adc_xec_dev_data_0, ctx),
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};
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DEVICE_AND_API_INIT(adc_xec, DT_INST_0_MICROCHIP_XEC_ADC_LABEL,
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adc_xec_init, &adc_xec_dev_data_0, NULL,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&adc_xec_api);
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@ -28,6 +28,13 @@ endif # PINMUX
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config GPIO
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default y
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if ADC
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config ADC_XEC
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default y
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endif # ADC
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if GPIO
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config GPIO_XEC
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