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dts: x86: configure different IO APIC delivery modes for various devices

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For HPET devices, configure it with fixed delivery mode because HPET
timer interrupt is needed to fuel the scheduler for all CPUS.

For all other type of devices, like UART, I2C, GPIO, Ethernet, etc.
configure them as lowest priority delivery mode, in which IO APIC
delivers the interrupt to the processor core that is executing at the
lowest priority among all the processors listed in the specified
destination. In this case, the device drivers can avoid the trouble of
handling repeated interrupts delivered to all CPUS.

Signed-off-by: Zide Chen <zide.chen@intel.com>
This commit is contained in:
Zide Chen 2020-03-04 16:01:39 -08:00 • committed by Anas Nashif
commit f32eeba925
7 changed files with 52 additions and 39 deletions
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8
boards/x86/gpmrb/gpmrb.dts
View file

@ -26,7 +26,7 @@
};
};
&uart0 { interrupts = <4 IRQ_TYPE_LEVEL_LOW 3>; };
&uart1 { interrupts = <5 IRQ_TYPE_LEVEL_LOW 3>; };
&uart2 { interrupts = <6 IRQ_TYPE_LEVEL_LOW 3>; };
&uart3 { interrupts = <7 IRQ_TYPE_LEVEL_LOW 3>; };
&uart0 { interrupts = <4 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; };
&uart1 { interrupts = <5 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; };
&uart2 { interrupts = <6 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; };
&uart3 { interrupts = <7 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; };

2
boards/x86/qemu_x86/qemu_x86.dts
View file

@ -41,7 +41,7 @@
compatible = "intel,e1000";
reg = <0xfebc0000 0x100>;
label = "eth0";
interrupts = <11 IRQ_TYPE_EDGE_RISING 3>;
interrupts = <11 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
interrupt-parent = <&intc>;
status = "okay";

46
dts/x86/apollo_lake.dtsi
View file

@ -49,7 +49,7 @@
label = "UART_0";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
current-speed = <115200>;
@ -63,7 +63,7 @@
label = "UART_1";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
@ -78,7 +78,7 @@
label = "UART_2";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
@ -93,7 +93,7 @@
label = "UART_3";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
@ -107,7 +107,7 @@
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x16,0) PCIE_ID(0x8086,0x5aac)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_0";
@ -121,7 +121,7 @@
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x16,1) PCIE_ID(0x8086,0x5aae)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_1";
@ -135,7 +135,7 @@
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x16,2) PCIE_ID(0x8086,0x5ab0)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_2";
@ -149,7 +149,7 @@
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x16,3) PCIE_ID(0x8086,0x5ab2)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_3";
@ -163,7 +163,7 @@
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x17,0) PCIE_ID(0x8086,0x5ab4)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_4";
@ -177,7 +177,7 @@
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x17,1) PCIE_ID(0x8086,0x5ab6)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_5";
@ -191,7 +191,7 @@
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x17,2) PCIE_ID(0x8086,0x5ab8)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_6";
@ -205,7 +205,7 @@
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,0x17,3) PCIE_ID(0x8086,0x5aba)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_7";
@ -215,7 +215,7 @@
gpio_n_000_031: gpio@d0c50000 {
compatible = "intel,apl-gpio";
reg = <0xd0c50000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_N_000";
@ -231,7 +231,7 @@
gpio_n_032_063: gpio@d0c50001 {
compatible = "intel,apl-gpio";
reg = <0xd0c50001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_N_032";
@ -247,7 +247,7 @@
gpio_n_064_077: gpio@d0c50002 {
compatible = "intel,apl-gpio";
reg = <0xd0c50002 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_N_064";
@ -263,7 +263,7 @@
gpio_nw_000_031: gpio@d0c40000 {
compatible = "intel,apl-gpio";
reg = <0xd0c40000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_NW_000";
@ -279,7 +279,7 @@
gpio_nw_032_063: gpio@d0c40001 {
compatible = "intel,apl-gpio";
reg = <0xd0c40001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_NW_032";
@ -295,7 +295,7 @@
gpio_nw_064_076: gpio@d0c40002 {
compatible = "intel,apl-gpio";
reg = <0xd0c40002 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_NW_064";
@ -311,7 +311,7 @@
gpio_w_000_031: gpio@d0c70000 {
compatible = "intel,apl-gpio";
reg = <0xd0c70000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_W_000";
@ -327,7 +327,7 @@
gpio_w_032_046: gpio@d0c70001 {
compatible = "intel,apl-gpio";
reg = <0xd0c70001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_W_032";
@ -343,7 +343,7 @@
gpio_sw_000_031: gpio@d0c00000 {
compatible = "intel,apl-gpio";
reg = <0xd0c00000 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_SW_000";
@ -360,7 +360,7 @@
gpio_sw_032_042: gpio@d0c00001 {
compatible = "intel,apl-gpio";
reg = <0xd0c00001 0x1000>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW 3>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "GPIO_SW_032";
@ -377,7 +377,7 @@
label = "HPET";
compatible = "intel,hpet";
reg = <0xfed00000 0x400>;
interrupts = <2 IRQ_TYPE_EDGE_RISING 4>;
interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
interrupt-parent = <&intc>;
status = "okay";

6
dts/x86/atom.dtsi
View file

@ -44,7 +44,7 @@
reg = <0x000003f8 0x100>;
label = "UART_0";
clock-frequency = <1843200>;
interrupts = <4 IRQ_TYPE_EDGE_RISING 3>;
interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
interrupt-parent = <&intc>;
status = "disabled";
@ -55,7 +55,7 @@
reg = <0x000002f8 0x100>;
label = "UART_1";
clock-frequency = <1843200>;
interrupts = <3 IRQ_TYPE_EDGE_RISING 3>;
interrupts = <3 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
interrupt-parent = <&intc>;
status = "disabled";
@ -65,7 +65,7 @@
label = "HPET";
compatible = "intel,hpet";
reg = <0xfed00000 0x400>;
interrupts = <2 IRQ_TYPE_EDGE_RISING 4>;
interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
interrupt-parent = <&intc>;
status = "disabled";

6
dts/x86/ia32.dtsi
View file

@ -44,7 +44,7 @@
reg = <0x000003f8 0x100>;
label = "UART_0";
clock-frequency = <1843200>;
interrupts = <4 IRQ_TYPE_EDGE_RISING 3>;
interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
interrupt-parent = <&intc>;
status = "disabled";
@ -55,7 +55,7 @@
reg = <0x000002f8 0x100>;
label = "UART_1";
clock-frequency = <1843200>;
interrupts = <3 IRQ_TYPE_EDGE_RISING 3>;
interrupts = <3 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
interrupt-parent = <&intc>;
status = "disabled";
@ -65,7 +65,7 @@
label = "HPET";
compatible = "intel,hpet";
reg = <0xfed00000 0x400>;
interrupts = <2 IRQ_TYPE_EDGE_RISING 4>;
interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
interrupt-parent = <&intc>;
status = "disabled";

2
dts/xtensa/intel/intel_s1000.dtsi
View file

@ -199,7 +199,7 @@
usb: usb@a0000 {
compatible = "snps,designware-usb";
reg = <0x000A0000 0x1000>;
interrupts = <0x07 IRQ_TYPE_EDGE_RISING 3>;
interrupts = <0x07 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
interrupt-parent = <&cavs0>;
num-bidir-endpoints = <6>;
label = "USB_0";

21
include/dt-bindings/interrupt-controller/intel-ioapic.h
View file

@ -10,9 +10,22 @@
#define IRQ_TYPE_EDGE 0x00000000
#define IRQ_TYPE_LOW 0x00002000
#define IRQ_TYPE_HIGH 0x00000000
#define IRQ_TYPE_EDGE_RISING (IRQ_TYPE_EDGE | IRQ_TYPE_HIGH)
#define IRQ_TYPE_EDGE_FALLING (IRQ_TYPE_EDGE | IRQ_TYPE_LOW)
#define IRQ_TYPE_LEVEL_HIGH (IRQ_TYPE_LEVEL | IRQ_TYPE_HIGH)
#define IRQ_TYPE_LEVEL_LOW (IRQ_TYPE_LEVEL | IRQ_TYPE_LOW)
#define IRQ_DELIVERY_LOWEST 0x00000100
#define IRQ_DELIVERY_FIXED 0x00000000
/*
* for most device interrupts, lowest priority delivery is preferred
* since this ensures only one CPU gets the interrupt in SMP systems.
*/
#define IRQ_TYPE_LOWEST_EDGE_RISING (IRQ_DELIVERY_LOWEST | IRQ_TYPE_EDGE | IRQ_TYPE_HIGH)
#define IRQ_TYPE_LOWEST_EDGE_FALLING (IRQ_DELIVERY_LOWEST | IRQ_TYPE_EDGE | IRQ_TYPE_LOW)
#define IRQ_TYPE_LOWEST_LEVEL_HIGH (IRQ_DELIVERY_LOWEST | IRQ_TYPE_LEVEL | IRQ_TYPE_HIGH)
#define IRQ_TYPE_LOWEST_LEVEL_LOW (IRQ_DELIVERY_LOWEST | IRQ_TYPE_LEVEL | IRQ_TYPE_LOW)
/* for interrupts that want to be delivered to all CPUs, e.g. HPET */
#define IRQ_TYPE_FIXED_EDGE_RISING (IRQ_DELIVERY_FIXED | IRQ_TYPE_EDGE | IRQ_TYPE_HIGH)
#define IRQ_TYPE_FIXED_EDGE_FALLING (IRQ_DELIVERY_FIXED | IRQ_TYPE_EDGE | IRQ_TYPE_LOW)
#define IRQ_TYPE_FIXED_LEVEL_HIGH (IRQ_DELIVERY_FIXED | IRQ_TYPE_LEVEL | IRQ_TYPE_HIGH)
#define IRQ_TYPE_FIXED_LEVEL_LOW (IRQ_DELIVERY_FIXED | IRQ_TYPE_LEVEL | IRQ_TYPE_LOW)
#endif