michaelh/zephyr
1
0
Fork 0
Code Releases Activity

arch: xtensa: Get CPU clock frequency from DTS

Browse source 
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit is contained in:
Piotr Zięcik 2019-04-11 14:28:52 +02:00 • committed by Carles Cufí
commit f2d84f08ff
5 changed files with 27 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

6
arch/xtensa/include/xtensa_rtos.h
View file

@ -46,10 +46,8 @@
#define XT_BOARD 1 #define XT_BOARD 1
#endif #endif
#ifdef CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC #undef XT_CLOCK_FREQ
#undef XT_CLOCK_FREQ #define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY
#define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
#endif
#ifndef XT_TIMER_INDEX #ifndef XT_TIMER_INDEX
#if defined configXT_TIMER_INDEX #if defined configXT_TIMER_INDEX

2
arch/xtensa/include/xtensa_timer.h
View file

@ -115,7 +115,7 @@
* anyway!). * anyway!).
*/ */
#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ) #if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
#define XT_CLOCK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC #define XT_CLOCK_FREQ DT_CPU_CLOCK_FREQUENCY
#endif #endif
#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD) #if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)

11
soc/xtensa/esp32/dts_fixup.h Normal file
View file

@ -0,0 +1,11 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
/* End of SoC Level DTS fixup file */

2
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -2,6 +2,8 @@
/* SoC level DTS fixup file */ /* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80800_BASE_ADDRESS #define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80800_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80800_CURRENT_SPEED #define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80800_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_80800_LABEL #define DT_UART_NS16550_PORT_0_NAME DT_NS16550_80800_LABEL

11
soc/xtensa/sample_controller/dts_fixup.h Normal file
View file

@ -0,0 +1,11 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_SAMPLE_CONTROLLER_0_CLOCK_FREQUENCY
/* End of SoC Level DTS fixup file */