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arch: xtensa: Get CPU clock frequency from DTS

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The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.

Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit is contained in:
Piotr Zięcik 2019-04-11 14:28:52 +02:00 • committed by Carles Cufí
commit f2d84f08ff
5 changed files with 27 additions and 5 deletions
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11
soc/xtensa/esp32/dts_fixup.h Normal file
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/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
/* End of SoC Level DTS fixup file */

2
soc/xtensa/intel_s1000/dts_fixup.h
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@ -2,6 +2,8 @@
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80800_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80800_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_80800_LABEL

11
soc/xtensa/sample_controller/dts_fixup.h Normal file
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/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_CPU_CLOCK_FREQUENCY DT_SAMPLE_CONTROLLER_0_CLOCK_FREQUENCY
/* End of SoC Level DTS fixup file */