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drivers/clock_control: Add clock_control on STM32L5 series

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Add clock_control driver for STM32L5.
It's based on L4/WB driver since it is similar IP.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2020-03-10 16:13:14 +01:00 • committed by Kumar Gala
commit f258199595
7 changed files with 36 additions and 18 deletions
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5
drivers/clock_control/CMakeLists.txt
View file

@ -26,8 +26,9 @@ else()
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X clock_stm32g0.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X clock_stm32g0.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X clock_stm32l0_l1.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X clock_stm32l0_l1.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l0_l1.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l0_l1.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4_wb.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4_l5_wb.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX clock_stm32l4_wb.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L5X clock_stm32l4_l5_wb.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX clock_stm32l4_l5_wb.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G4X clock_stm32g4.c) zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G4X clock_stm32g4.c)
endif() endif()
endif() endif()

6
drivers/clock_control/Kconfig.stm32
View file

@ -39,7 +39,7 @@ config CLOCK_STM32_SYSCLK_SRC_HSI
config CLOCK_STM32_SYSCLK_SRC_MSI config CLOCK_STM32_SYSCLK_SRC_MSI
bool "MSI" bool "MSI"
depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX
help help
Use MSI as source of SYSCLK Use MSI as source of SYSCLK
@ -89,7 +89,7 @@ choice
config CLOCK_STM32_PLL_SRC_MSI config CLOCK_STM32_PLL_SRC_MSI
bool "MSI" bool "MSI"
depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX
help help
Use MSI as source of PLL Use MSI as source of PLL
@ -120,7 +120,7 @@ source "drivers/clock_control/Kconfig.stm32f1"
source "drivers/clock_control/Kconfig.stm32f2_f4_f7" source "drivers/clock_control/Kconfig.stm32f2_f4_f7"
source "drivers/clock_control/Kconfig.stm32h7" source "drivers/clock_control/Kconfig.stm32h7"
source "drivers/clock_control/Kconfig.stm32l0_l1" source "drivers/clock_control/Kconfig.stm32l0_l1"
source "drivers/clock_control/Kconfig.stm32l4_wb" source "drivers/clock_control/Kconfig.stm32l4_l5_wb"
source "drivers/clock_control/Kconfig.stm32g0" source "drivers/clock_control/Kconfig.stm32g0"
source "drivers/clock_control/Kconfig.stm32g4" source "drivers/clock_control/Kconfig.stm32g4"

6
drivers/clock_control/Kconfig.stm32l4_wb → drivers/clock_control/Kconfig.stm32l4_l5_wb
View file

@ -1,9 +1,9 @@
# STM32L4 and STM32WB PLL configuration options # STM32L4, STM32L5 and STM32WB PLL configuration options
# Copyright (c) 2019 Linaro # Copyright (c) 2019 Linaro
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX
config CLOCK_STM32_PLL_M_DIVISOR config CLOCK_STM32_PLL_M_DIVISOR
int "PLL divisor" int "PLL divisor"
@ -59,4 +59,4 @@ config CLOCK_STM32_MSI_PLL_MODE
help help
Enable hardware auto-calibration with LSE. Enable hardware auto-calibration with LSE.
endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX

20
drivers/clock_control/clock_stm32_ll_common.c
View file

@ -88,6 +88,7 @@ static inline int stm32_clock_control_on(struct device *dev,
LL_AHB1_GRP1_EnableClock(pclken->enr); LL_AHB1_GRP1_EnableClock(pclken->enr);
break; break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) || \ defined(CONFIG_SOC_SERIES_STM32F4X) || \
defined(CONFIG_SOC_SERIES_STM32F7X) || \ defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32F2X) || \ defined(CONFIG_SOC_SERIES_STM32F2X) || \
@ -96,21 +97,19 @@ static inline int stm32_clock_control_on(struct device *dev,
case STM32_CLOCK_BUS_AHB2: case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_EnableClock(pclken->enr); LL_AHB2_GRP1_EnableClock(pclken->enr);
break; break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X || #endif /* CONFIG_SOC_SERIES_STM32_* */
CONFIG_SOC_SERIES_STM32F7X || CONFIG_SOC_SERIES_STM32F2X ||
CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
case STM32_CLOCK_BUS_APB1: case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_EnableClock(pclken->enr); LL_APB1_GRP1_EnableClock(pclken->enr);
break; break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \ defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32G4X) defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_APB1_2: case STM32_CLOCK_BUS_APB1_2:
LL_APB1_GRP2_EnableClock(pclken->enr); LL_APB1_GRP2_EnableClock(pclken->enr);
break; break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X || #endif /* CONFIG_SOC_SERIES_STM32_* */
CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
#if !defined(CONFIG_SOC_SERIES_STM32F0X) #if !defined(CONFIG_SOC_SERIES_STM32F0X)
case STM32_CLOCK_BUS_APB2: case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_EnableClock(pclken->enr); LL_APB2_GRP1_EnableClock(pclken->enr);
@ -141,6 +140,7 @@ static inline int stm32_clock_control_off(struct device *dev,
LL_AHB1_GRP1_DisableClock(pclken->enr); LL_AHB1_GRP1_DisableClock(pclken->enr);
break; break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) || \ defined(CONFIG_SOC_SERIES_STM32F4X) || \
defined(CONFIG_SOC_SERIES_STM32F7X) || \ defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32F2X) || \ defined(CONFIG_SOC_SERIES_STM32F2X) || \
@ -148,20 +148,19 @@ static inline int stm32_clock_control_off(struct device *dev,
case STM32_CLOCK_BUS_AHB2: case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_DisableClock(pclken->enr); LL_AHB2_GRP1_DisableClock(pclken->enr);
break; break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X || #endif /* CONFIG_SOC_SERIES_STM32_* */
CONFIG_SOC_SERIES_STM32F7X || CONFIG_SOC_SERIES_STM32G4X */
case STM32_CLOCK_BUS_APB1: case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_DisableClock(pclken->enr); LL_APB1_GRP1_DisableClock(pclken->enr);
break; break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \ defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32G4X) defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_APB1_2: case STM32_CLOCK_BUS_APB1_2:
LL_APB1_GRP2_DisableClock(pclken->enr); LL_APB1_GRP2_DisableClock(pclken->enr);
break; break;
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X || #endif /* CONFIG_SOC_SERIES_STM32_* */
CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
#if !defined(CONFIG_SOC_SERIES_STM32F0X) #if !defined(CONFIG_SOC_SERIES_STM32F0X)
case STM32_CLOCK_BUS_APB2: case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_DisableClock(pclken->enr); LL_APB2_GRP1_DisableClock(pclken->enr);
@ -211,11 +210,12 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
break; break;
case STM32_CLOCK_BUS_APB1: case STM32_CLOCK_BUS_APB1:
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ #if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \ defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32G4X) defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_APB1_2: case STM32_CLOCK_BUS_APB1_2:
#endif #endif /* CONFIG_SOC_SERIES_STM32_* */
#if defined(CONFIG_SOC_SERIES_STM32G0X) #if defined(CONFIG_SOC_SERIES_STM32G0X)
case STM32_CLOCK_BUS_APB2: case STM32_CLOCK_BUS_APB2:
/* /*

0
drivers/clock_control/clock_stm32l4_wb.c → drivers/clock_control/clock_stm32l4_l5_wb.c
View file

9
dts/arm/st/l5/stm32l5.dtsi
View file

@ -6,6 +6,7 @@
#include <arm/armv8-m.dtsi> #include <arm/armv8-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
/ { / {
cpus { cpus {
@ -46,6 +47,14 @@
label = "FLASH_STM32"; label = "FLASH_STM32";
}; };
}; };
rcc: rcc@40021000 {
compatible = "st,stm32-rcc";
clocks-controller;
#clock-cells = <2>;
reg = <0x40021000 0x400>;
label = "STM32_CLK_RCC";
};
}; };
}; };

8
soc/arm/st_stm32/stm32l5/soc.h
View file

@ -27,6 +27,14 @@
/* Add include for DTS generated information */ /* Add include for DTS generated information */
#include <devicetree.h> #include <devicetree.h>
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
#include <stm32l5xx_ll_utils.h>
#include <stm32l5xx_ll_bus.h>
#include <stm32l5xx_ll_rcc.h>
#include <stm32l5xx_ll_system.h>
#include <stm32l5xx_ll_pwr.h>
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
#endif /* !_ASMLANGUAGE */ #endif /* !_ASMLANGUAGE */
#endif /* _STM32L5_SOC_H_ */ #endif /* _STM32L5_SOC_H_ */