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soc: esp32: riscv: fix interrupt allocator

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Current interrupt allocator is not taking into account
reserved areas. In case of esp32c6, Wi-Fi isn't properly
configured, causing instability or even non-functional feature.
This adds the reserved area ranges for all risc-v based SoC and
unify the slot finding based on interrupt source.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is contained in:
Sylvio Alves 2025-03-01 16:24:33 -03:00 • committed by Fabio Baltieri
commit f22de9733b
3 changed files with 118 additions and 132 deletions
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6
soc/espressif/esp32c6/soc_irq.c
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@ -53,7 +53,7 @@ int arch_irq_is_enabled(unsigned int irq)
uint32_t soc_intr_get_next_source(void)
{
uint32_t status;
uint32_t source;
uint32_t source = IRQ_NA;
/* Status register for interrupt sources 0 ~ 31 */
status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_0_REG) &
@ -77,7 +77,9 @@ uint32_t soc_intr_get_next_source(void)
status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_2_REG) &
esp_intr_get_enabled_intmask(2);
source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_REG2_THRESHOLD);
if (status) {
source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_REG2_THRESHOLD);
}
ret:
return source;