soc: nxp: kv5x: move clk divider options to device tree

Use kinetis SIM clock divider options set in device tree
instead of kconfig.

The kv5x device tree originally used the undefined
"nxp,kv58-mcg" binding for the MCG node. This has been
replaced by the general "nxp,kinetis-mcg" binding.

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>

dts/arm/nxp/nxp_kv5x.dtsi

@@ -6,6 +6,7 @@
 
 #include <arm/armv7-m.dtsi>
 #include <dt-bindings/clock/kinetis_sim.h>
+#include <dt-bindings/clock/kinetis_mcg.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/i2c/i2c.h>
 
@@ -37,12 +38,41 @@
 			reg = <0x40047000 0x2000>;
 			label = "SIM";
 			#clock-cells = <3>;
+
+			core_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <1>;
+				#clock-cells = <0>;
+			};
+
+			bus_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <2>;
+				#clock-cells = <0>;
+			};
+
+			flexbus_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <4>;
+				#clock-cells = <0>;
+			};
+
+			flash_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&mcg KINETIS_MCG_OUT_CLK>;
+				clock-div = <10>;
+				#clock-cells = <0>;
+			};
 		};
 
 		mcg: clock-controller@40064000 {
-			compatible = "nxp,kv58-mcg";
+			compatible = "nxp,kinetis-mcg";
 			reg = <0x40064000 0x1000>;
-			system-clock-frequency = <240000000>;
+			label = "MCG";
+			#clock-cells = <1>;
 		};
 
 		osc: clock-controller@40065000 {

soc/arm/nxp_kinetis/kv5x/Kconfig.soc

@@ -57,32 +57,4 @@ config SOC_PART_NUMBER_KINETIS_KV5X
 	  number selection choice defines the default value for this
 	  string.
 
-config KV5X_CORE_CLOCK_DIVIDER
-	int "Freescale KV5x core clock divider"
-	default 1
-	help
-	  This option specifies the divide value for the KV5X processor core clock
-	  from the system clock.
-
-config KV5X_BUS_CLOCK_DIVIDER
-	int "Freescale KV5x bus clock divider"
-	default 2
-	help
-	  This option specifies the divide value for the KV5X bus clock from the
-	  system clock.
-
-config KV5X_FLEXBUS_CLOCK_DIVIDER
-	int "Freescale KV5x FlexBus clock divider"
-	default 4
-	help
-	  This option specifies the divide value for the KV5X FlexBus clock from the
-	  system clock.
-
-config KV5X_FLASH_CLOCK_DIVIDER
-	int "Freescale KV5x flash clock divider"
-	default 10
-	help
-	  This option specifies the divide value for the KV5X flash clock from the
-	  system clock.
-
 endif # SOC_SERIES_KINETIS_KV5X

soc/arm/nxp_kinetis/kv5x/soc.c

@@ -18,6 +18,12 @@
 #define RUNM_VLPR		(2)
 #define RUNM_HSRUN		(3)
 
+#define CLOCK_NODEID(clk) \
+	DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
+
+#define CLOCK_DIVIDER(clk) \
+	DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
+
 static const osc_config_t osc_config = {
 	.freq = CONFIG_OSC_XTAL0_FREQ,
 	.capLoad = 0,
@@ -50,10 +56,10 @@ static const mcg_pll_config_t pll0_config = {
 static const sim_clock_config_t sim_config = {
 	.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
 	.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
-	.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_KV5X_CORE_CLOCK_DIVIDER - 1) |
+	.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
-		   SIM_CLKDIV1_OUTDIV2(CONFIG_KV5X_BUS_CLOCK_DIVIDER - 1) |
+		   SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
-		   SIM_CLKDIV1_OUTDIV3(CONFIG_KV5X_FLEXBUS_CLOCK_DIVIDER - 1) |
+		   SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
-		   SIM_CLKDIV1_OUTDIV4(CONFIG_KV5X_FLASH_CLOCK_DIVIDER - 1),
+		   SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
 };
 
 static ALWAYS_INLINE void clk_init(void)