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arm64: FPU context switching support

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This adds FPU sharing support with a lazy context switching algorithm.

Every thread is allowed to use FPU/SIMD registers. In fact, the compiler
may insert FPU reg accesses in anycontext to optimize even non-FP code
unless the -mgeneral-regs-only compiler flag is used, but Zephyr
currently doesn't support such a build.

It is therefore possible to do FP access in IRS as well with this patch
although IRQs are then disabled to prevent nested IRQs in such cases.

Because the thread object grows in size, some tests have to be adjusted.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2021-04-07 23:31:44 -04:00 • committed by Carles Cufí
commit f1f63dda17
20 changed files with 588 additions and 5 deletions
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4
include/arch/arm64/structs.h
View file

@ -9,7 +9,9 @@
/* Per CPU architecture specifics */
struct _cpu_arch {
/* content coming soon */
#ifdef CONFIG_FPU_SHARING
struct k_thread *fpu_owner;
#endif
};
#endif /* ZEPHYR_INCLUDE_ARM64_STRUCTS_H_ */

11
include/arch/arm64/thread.h
View file

@ -40,9 +40,20 @@ struct _callee_saved {
typedef struct _callee_saved _callee_saved_t;
struct z_arm64_fp_context {
__int128 q0, q1, q2, q3, q4, q5, q6, q7;
__int128 q8, q9, q10, q11, q12, q13, q14, q15;
__int128 q16, q17, q18, q19, q20, q21, q22, q23;
__int128 q24, q25, q26, q27, q28, q29, q30, q31;
uint32_t fpsr, fpcr;
};
struct _thread_arch {
#ifdef CONFIG_USERSPACE
struct arm_mmu_ptables *ptables;
#endif
#ifdef CONFIG_FPU_SHARING
struct z_arm64_fp_context saved_fp_context;
#endif
uint8_t exception_depth;
};