drivers: can: Implement stm32fd driver
This driver is the SoC specific implementation of the Bosch M_CAN IP. Signed-off-by: Alexander Wachter <alexander@wachter.cloud>
This commit is contained in:
Alexander Wachter
Kumar Gala
parent
1c50ef6c43
commit
f1754b19eb
6 changed files with 357 additions and 34 deletions
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@ -5,20 +5,287 @@
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*/
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#include <drivers/can.h>
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#include <kernel.h>
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#include <soc.h>
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#include <stm32_ll_rcc.h>
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#include "can_stm32fd.h"
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#include <pinmux/stm32/pinmux_stm32.h>
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u32_t can_mcan_get_core_clock(struct device *dev)
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{
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u32_t core_clock = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE);
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u32_t dbrp, nbrp;
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#include <logging/log.h>
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LOG_MODULE_DECLARE(can_driver, CONFIG_CAN_LOG_LEVEL);
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#if CONFIG_CAN_CKDIV != 0
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core_clock /= CONFIG_CAN_CKDIV * 2;
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#if CONFIG_CAN_STM32_CLOCK_DIVISOR != 1 && CONFIG_CAN_STM32_CLOCK_DIVISOR & 0x01
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#error CAN_STM32_CLOCK_DIVISOR invalid.\
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Allowed values are 1 or 2 * n, where n <= 15
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#endif
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__weak void can_mcan_clock_enable()
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#define DT_DRV_COMPAT st_stm32_fdcan
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int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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ARG_UNUSED(dev);
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int rate_tmp;
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rate_tmp = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE);
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if (rate_tmp == LL_RCC_PERIPH_FREQUENCY_NO) {
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LOG_ERR("Can't read core clock");
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return -EIO;
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}
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*rate = rate_tmp / CONFIG_CAN_STM32_CLOCK_DIVISOR;
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return 0;
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}
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void can_stm32fd_clock_enable(void)
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{
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LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1);
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__HAL_RCC_FDCAN_CLK_ENABLE();
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FDCAN_CONFIG->CKDIV = CONFIG_CAN_CKDIV;
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FDCAN_CONFIG->CKDIV = CONFIG_CAN_STM32_CLOCK_DIVISOR >> 1;
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}
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void can_stm32fd_register_state_change_isr(const struct device *dev,
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can_state_change_isr_t isr)
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{
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struct can_stm32fd_data *data = DEV_DATA(dev);
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data->mcan_data.state_change_isr = isr;
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}
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static int can_stm32fd_init(const struct device *dev)
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{
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const struct can_stm32fd_config *cfg = DEV_CFG(dev);
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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struct can_mcan_data *mcan_data = &DEV_DATA(dev)->mcan_data;
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struct can_mcan_msg_sram *msg_ram = cfg->msg_sram;
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int ret;
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/* Configure dt provided device signals when available */
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ret = stm32_dt_pinctrl_configure(cfg->pinctrl,
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ARRAY_SIZE(cfg->pinctrl),
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(uint32_t)mcan_cfg->can);
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if (ret < 0) {
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LOG_ERR("CAN pinctrl setup failed (%d)", ret);
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return ret;
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}
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can_stm32fd_clock_enable();
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ret = can_mcan_init(dev, mcan_cfg, msg_ram, mcan_data);
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if (ret) {
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return ret;
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}
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cfg->config_irq();
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return ret;
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}
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enum can_state can_stm32fd_get_state(const struct device *dev,
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struct can_bus_err_cnt *err_cnt)
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{
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const struct can_stm32fd_config *cfg = DEV_CFG(dev);
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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return can_mcan_get_state(mcan_cfg, err_cnt);
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}
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int can_stm32fd_send(const struct device *dev, const struct zcan_frame *frame,
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k_timeout_t timeout, can_tx_callback_t callback,
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void *callback_arg)
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{
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const struct can_stm32fd_config *cfg = DEV_CFG(dev);
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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struct can_mcan_data *mcan_data = &DEV_DATA(dev)->mcan_data;
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struct can_mcan_msg_sram *msg_ram = cfg->msg_sram;
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return can_mcan_send(mcan_cfg, mcan_data, msg_ram, frame, timeout,
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callback, callback_arg);
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}
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int can_stm32fd_attach_isr(const struct device *dev, can_rx_callback_t isr,
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void *cb_arg, const struct zcan_filter *filter)
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{
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const struct can_stm32fd_config *cfg = DEV_CFG(dev);
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struct can_mcan_data *mcan_data = &DEV_DATA(dev)->mcan_data;
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struct can_mcan_msg_sram *msg_ram = cfg->msg_sram;
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return can_mcan_attach_isr(mcan_data, msg_ram, isr, cb_arg, filter);
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}
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void can_stm32fd_detach(const struct device *dev, int filter_nr)
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{
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const struct can_stm32fd_config *cfg = DEV_CFG(dev);
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struct can_mcan_data *mcan_data = &DEV_DATA(dev)->mcan_data;
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struct can_mcan_msg_sram *msg_ram = cfg->msg_sram;
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can_mcan_detach(mcan_data, msg_ram, filter_nr);
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}
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int can_stm32fd_set_mode(const struct device *dev, enum can_mode mode)
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{
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const struct can_stm32fd_config *cfg = DEV_CFG(dev);
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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return can_mcan_set_mode(mcan_cfg, mode);
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}
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int can_stm32fd_set_timing(const struct device *dev,
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const struct can_timing *timing,
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const struct can_timing *timing_data)
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{
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const struct can_stm32fd_config *cfg = DEV_CFG(dev);
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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return can_mcan_set_timing(mcan_cfg, timing, timing_data);
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}
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void can_stm32fd_line_0_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct can_stm32fd_config *cfg = DEV_CFG(dev);
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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struct can_stm32fd_data *data = DEV_DATA(dev);
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struct can_mcan_data *mcan_data = &data->mcan_data;
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struct can_mcan_msg_sram *msg_ram = cfg->msg_sram;
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can_mcan_line_0_isr(mcan_cfg, msg_ram, mcan_data);
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}
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void can_stm32fd_line_1_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct can_stm32fd_config *cfg = DEV_CFG(dev);
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const struct can_mcan_config *mcan_cfg = &cfg->mcan_cfg;
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struct can_mcan_data *mcan_data = &DEV_DATA(dev)->mcan_data;
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struct can_mcan_msg_sram *msg_ram = cfg->msg_sram;
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can_mcan_line_1_isr(mcan_cfg, msg_ram, mcan_data);
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}
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static const struct can_driver_api can_api_funcs = {
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.set_mode = can_stm32fd_set_mode,
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.set_timing = can_stm32fd_set_timing,
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.send = can_stm32fd_send,
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.attach_isr = can_stm32fd_attach_isr,
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.detach = can_stm32fd_detach,
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.get_state = can_stm32fd_get_state,
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#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
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.recover = can_mcan_recover,
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#endif
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.get_core_clock = can_stm32fd_get_core_clock,
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.register_state_change_isr = can_stm32fd_register_state_change_isr,
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.timing_min = {
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.sjw = 0x7f,
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.prop_seg = 0x00,
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.phase_seg1 = 0x01,
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.phase_seg2 = 0x01,
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.prescaler = 0x01
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},
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.timing_max = {
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.sjw = 0x7f,
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.prop_seg = 0x00,
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.phase_seg1 = 0x100,
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.phase_seg2 = 0x80,
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.prescaler = 0x200
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},
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#ifdef CONFIG_CAN_FD_MODE
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.timing_min_data = {
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.sjw = 0x01,
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.prop_seg = 0x01,
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.phase_seg1 = 0x01,
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.phase_seg2 = 0x01,
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.prescaler = 0x01
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},
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.timing_max_data = {
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.sjw = 0x10,
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.prop_seg = 0x00,
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.phase_seg1 = 0x20,
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.phase_seg2 = 0x10,
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.prescaler = 0x20
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}
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#endif
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};
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#define CAN_STM32FD_IRQ_CFG_FUNCTION(inst) \
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static void config_can_##inst##_irq(void) \
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{ \
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LOG_DBG("Enable CAN" #inst " IRQ"); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_0, irq), \
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DT_INST_IRQ_BY_NAME(inst, line_0, priority), \
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can_stm32fd_line_0_isr, DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(inst, line_0, irq)); \
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_1, irq), \
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DT_INST_IRQ_BY_NAME(inst, line_1, priority), \
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can_stm32fd_line_1_isr, DEVICE_DT_INST_GET(inst), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(inst, line_1, irq)); \
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}
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#ifdef CONFIG_CAN_FD_MODE
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#define CAN_STM32FD_CFG_INST(inst) \
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static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
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.msg_sram = (struct can_mcan_msg_sram *) \
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DT_INST_REG_ADDR_BY_NAME(inst, message_ram), \
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.config_irq = config_can_##inst##_irq, \
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.mcan_cfg = { \
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.can = (struct can_mcan_reg *) \
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DT_INST_REG_ADDR_BY_NAME(inst, m_can), \
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.bus_speed = DT_INST_PROP(inst, bus_speed), \
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.sjw = DT_INST_PROP(inst, sjw), \
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.sample_point = DT_INST_PROP_OR(inst, sample_point, 0), \
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.prop_ts1 = DT_INST_PROP_OR(inst, prop_seg, 0) + \
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DT_INST_PROP_OR(inst, phase_seg1, 0), \
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.ts2 = DT_INST_PROP_OR(inst, phase_seg2, 0), \
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.bus_speed_data = DT_INST_PROP(inst, bus_speed_data), \
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.sjw_data = DT_INST_PROP(inst, sjw_data), \
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.sample_point_data = \
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DT_INST_PROP_OR(inst, sample_point_data, 0), \
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.prop_ts1_data = DT_INST_PROP_OR(inst, prop_seg_data, 0) + \
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DT_INST_PROP_OR(inst, phase_seg1_data, 0), \
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.ts2_data = DT_INST_PROP_OR(inst, phase_seg2_data, 0), \
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.tx_delay_comp_offset = \
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DT_INST_PROP(inst, tx_delay_comp_offset) \
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}, \
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.pinctrl = ST_STM32_DT_INST_PINCTRL(inst, 0), \
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};
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#else /* CONFIG_CAN_FD_MODE */
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#define CAN_STM32FD_CFG_INST(inst) \
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static const struct can_stm32fd_config can_stm32fd_cfg_##inst = { \
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.msg_sram = (struct can_mcan_msg_sram *) \
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DT_INST_REG_ADDR_BY_NAME(inst, message_ram), \
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.config_irq = config_can_##inst##_irq, \
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.mcan_cfg = { \
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.can = (struct can_mcan_reg *) \
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DT_INST_REG_ADDR_BY_NAME(inst, m_can), \
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.bus_speed = DT_INST_PROP(inst, bus_speed), \
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.sjw = DT_INST_PROP(inst, sjw), \
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.sample_point = DT_INST_PROP_OR(inst, sample_point, 0), \
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.prop_ts1 = DT_INST_PROP_OR(inst, prop_seg, 0) + \
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DT_INST_PROP_OR(inst, phase_seg1, 0), \
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.ts2 = DT_INST_PROP_OR(inst, phase_seg2, 0), \
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}, \
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.pinctrl = ST_STM32_DT_INST_PINCTRL(inst, 0), \
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};
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#endif /* CONFIG_CAN_FD_MODE */
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#define CAN_STM32FD_DATA_INST(inst) \
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static struct can_stm32fd_data can_stm32fd_dev_data_##inst;
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#define CAN_STM32FD_DEVICE_INST(inst) \
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DEVICE_DT_INST_DEFINE(inst, &can_stm32fd_init, NULL, \
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&can_stm32fd_dev_data_##inst, &can_stm32fd_cfg_##inst, \
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&can_api_funcs);
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#define CAN_STM32FD_INST(inst) \
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CAN_STM32FD_IRQ_CFG_FUNCTION(inst) \
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CAN_STM32FD_CFG_INST(inst) \
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CAN_STM32FD_DATA_INST(inst) \
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CAN_STM32FD_DEVICE_INST(inst)
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DT_INST_FOREACH_STATUS_OKAY(CAN_STM32FD_INST)
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