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boards: nordic: add initial support for nRF9280 PDK

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Add board support for Application, Radio and PPR cores
of the nRF9230 SoC / nRF9280 SiP on the nRF9280 PDK board.

Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Co-authored-by: Andreas Moltumyr <andreas.moltumyr@nordicsemi.no>
This commit is contained in:
Emanuele Di Santo 2024-08-02 13:35:19 +02:00 • committed by Anas Nashif
commit f156dd7d0c
22 changed files with 1384 additions and 0 deletions
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24
boards/nordic/nrf9280pdk/Kconfig.defconfig Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if BOARD_NRF9280PDK_NRF9280_CPUAPP
config BT_HCI_IPC
default y if BT
endif # BOARD_NRF9280PDK_NRF9280_CPUAPP
if BOARD_NRF9280PDK_NRF9280_CPURAD
config BT_CTLR
default y if BT
endif # BOARD_NRF9280PDK_NRF9280_CPURAD
if BOARD_NRF9280PDK_NRF9280_CPUPPR
# As PPR has limited memory most of tests does not fit with asserts enabled.
config ASSERT
default n if ZTEST
endif # BOARD_NRF9280PDK_NRF9280_CPUPPR

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boards/nordic/nrf9280pdk/Kconfig.nrf9280pdk Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config BOARD_NRF9280PDK
select SOC_NRF9280_CPUAPP if BOARD_NRF9280PDK_NRF9280_CPUAPP
select SOC_NRF9280_CPURAD if BOARD_NRF9280PDK_NRF9280_CPURAD
select SOC_NRF9280_CPUPPR if BOARD_NRF9280PDK_NRF9280_CPUPPR || \
BOARD_NRF9280PDK_NRF9280_CPUPPR_XIP

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boards/nordic/nrf9280pdk/board.cmake Normal file
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# SPDX-License-Identifier: Apache-2.0
include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
if(CONFIG_BOARD_NRF9280PDK_NRF9280_CPUAPP OR CONFIG_BOARD_NRF9280PDK_NRF9280_CPURAD)
if(CONFIG_BOARD_NRF9280PDK_NRF9280_CPUAPP)
set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf9280_cpuapp.JLinkScript)
else()
set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf9280_cpurad.JLinkScript)
endif()
board_runner_args(jlink "--device=CORTEX-M33" "--speed=4000" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
endif()

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boards/nordic/nrf9280pdk/board.yml Normal file
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board:
name: nrf9280pdk
vendor: nordic
socs:
- name: nrf9280
variants:
- name: xip
cpucluster: cpuppr

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boards/nordic/nrf9280pdk/doc/index.rst Normal file
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.. _nrf9280pdk_nrf9280:
nRF9280 PDK
###########
Overview
********
.. note::
All software for the nRF9280 SiP is experimental and hardware availability
is restricted to the participants in the limited sampling program.
The nRF9280 DK is a single-board development kit for evaluation and development
on the Nordic nRF9280 System-in-Package (SiP).
The nRF9280 is a multicore SiP with:
* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
Extensions, running at up to 320 MHz, referred to as the **application core**
* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
Extensions, running at up to 256 MHz, referred to as the **radio core**.
The ``nrf9280pdk/nrf9280/cpuapp`` board target provides support for
the application core on the nRF9280 SiP.
The ``nrf9280pdk/nrf9280/cpurad`` board target provides support for
the radio core on the nRF9280 SiP.
The ``nrf9280pdk/nrf9280/cpuppr`` board target provides support for
the PPR core on the nRF9280 SiP.
nRF9280 SiP provides support for the following devices:
* :abbr:`ADC (Analog to Digital Converter)`
* CLOCK
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`GRTC (Global real-time counter)`
* :abbr:`I2C (Inter-Integrated Circuit)`
* MRAM
* :abbr:`PWM (Pulse Width Modulation)`
* RADIO (Bluetooth Low Energy and 802.15.4)
* :abbr:`SPI (Serial Peripheral Interface)`
* :abbr:`UART (Universal asynchronous receiver-transmitter)`
* :abbr:`USB (Universal Serial Bus)`
* :abbr:`WDT (Watchdog Timer)`
Hardware
********
nRF9280 DK has two crystal oscillators:
* High-frequency 32 MHz crystal oscillator (HFXO)
* Low-frequency 32.768 kHz crystal oscillator (LFXO)
Supported Features
==================
The ``nrf9280pdk/nrf9280/cpuapp`` board target supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| GRTC | on-chip | system clock |
+-----------+------------+----------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+----------------------+
| PWM | on-chip | pwm |
+-----------+------------+----------------------+
| SPI(M/S) | on-chip | spi |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| WDT | on-chip | watchdog |
+-----------+------------+----------------------+
The ``nrf9280pdk/nrf9280/cpurad`` board target supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| GRTC | on-chip | system clock |
+-----------+------------+----------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+----------------------+
| SPI(M/S) | on-chip | spi |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| WDT | on-chip | watchdog |
+-----------+------------+----------------------+
The ``nrf9280pdk/nrf9280/cpuppr`` board target supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| GRTC | on-chip | system clock |
+-----------+------------+----------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+----------------------+
| SPI(M/S) | on-chip | spi |
+-----------+------------+----------------------+
| PWM | on-chip | pwm |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
Connections and IOs
===================
LEDs
----
* LED1 (green) = P9.02
* LED2 (green) = P9.03
* LED3 (green) = P9.04
* LED4 (green) = P9.05
Push buttons
------------
* BUTTON1 = P0.8
* BUTTON2 = P0.9
* BUTTON3 = P0.10
* BUTTON4 = P0.11
* RESET (SW1)
Programming and Debugging
*************************
Applications for both the ``nrf9280pdk/nrf9280/cpuapp`` and
``nrf9280pdk/nrf9280/cpurad`` board targets can be built, flashed,
and debugged in the usual way. See :ref:`build_an_application`
and :ref:`application_run` for more details on building and running.
Flashing
========
As an example, this section shows how to build and flash the :ref:`hello_world`
application.
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software. Further information can be
found in :ref:`nordic_segger_flashing`.
To build and program the sample to the nRF9280 DK, complete the following steps:
1. Connect the nRF9280 DK to your computer using the IMCU USB port on the DK.
#. Build the sample by running the following command:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nrf9280pdk/nrf9280/cpuapp
:goals: build flash
Testing the LEDs and buttons in the nRF9280 DK
***********************************************
There are 2 samples that allow you to test that the buttons (switches) and LEDs
on the board are working properly with Zephyr:
* :zephyr:code-sample:`blinky`
* :zephyr:code-sample:`button`
You can build and flash the examples to make sure Zephyr is running correctly on
your board. The button and LED definitions can be found in
:zephyr_file:`boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts`.

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boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-ipc_conf.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
ipc {
cpusec_cpuapp_ipc: ipc-1-2 {
compatible = "zephyr,ipc-icmsg";
status = "disabled";
mboxes = <&cpusec_bellboard 12>,
<&cpuapp_bellboard 0>;
};
cpusec_cpurad_ipc: ipc-1-3 {
compatible = "zephyr,ipc-icmsg";
status = "disabled";
mboxes = <&cpusec_bellboard 18>,
<&cpurad_bellboard 0>;
};
cpuapp_cpurad_ipc: ipc-2-3 {
compatible = "zephyr,ipc-icbmsg";
status = "disabled";
mboxes = <&cpuapp_bellboard 18>,
<&cpurad_bellboard 12>;
};
cpuapp_cpusys_ipc: ipc-2-12 {
compatible = "zephyr,ipc-icmsg";
status = "disabled";
mboxes = <&cpuapp_bellboard 6>,
<&cpusys_vevif 12>;
};
cpuapp_cpuppr_ipc: ipc-2-13 {
compatible = "zephyr,ipc-icmsg";
status = "disabled";
mboxes = <&cpuapp_bellboard 13>,
<&cpuppr_vevif 12>;
};
cpurad_cpusys_ipc: ipc-3-12 {
compatible = "zephyr,ipc-icmsg";
status = "disabled";
mboxes = <&cpurad_bellboard 6>,
<&cpusys_vevif 18>;
};
};
};

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boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
/ {
reserved-memory {
/* The first 64kb are reserved for SecDom.
* The next 4kb are reserved for IPC between SecDom and Cellcore.
*/
cpurad_ram0x_region: memory@2f011000 {
compatible = "nordic,owned-memory";
reg = <0x2f011000 DT_SIZE_K(4)>;
status = "disabled";
perm-read;
perm-write;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2f011000 0x1000>;
cpusec_cpurad_ipc_shm: memory@0 {
reg = <0x0 DT_SIZE_K(2)>;
};
cpurad_cpusec_ipc_shm: memory@800 {
reg = <0x800 DT_SIZE_K(2)>;
};
};
cpuapp_ram0x_region: memory@2f012000 {
compatible = "nordic,owned-memory";
reg = <0x2f012000 DT_SIZE_K(516)>;
status = "disabled";
perm-read;
perm-write;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2f012000 0x81000>;
cpusec_cpuapp_ipc_shm: memory@0 {
reg = <0x0 DT_SIZE_K(2)>;
};
cpuapp_cpusec_ipc_shm: memory@800 {
reg = <0x800 DT_SIZE_K(2)>;
};
cpuapp_data: memory@1000 {
reg = <0x1000 DT_SIZE_K(512)>;
};
};
cpuapp_cpurad_ram0x_region: memory@2f0cf000 {
compatible = "nordic,owned-memory";
reg = <0x2f0cf000 DT_SIZE_K(4)>;
status = "disabled";
perm-read;
perm-write;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2f0cf000 0x1000>;
cpuapp_cpurad_ipc_shm: memory@0 {
reg = <0x0 DT_SIZE_K(2)>;
};
cpurad_cpuapp_ipc_shm: memory@800 {
reg = <0x800 DT_SIZE_K(2)>;
};
};
cpuapp_cpucell_ram0x_region: memory@2f0d0000 {
reg = <0x2f0d0000 DT_SIZE_K(36)>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2f0d0000 0x9000>;
/* Control region, with ICmsg buffers.
* Size is fixed.
*/
cpuapp_cpucell_ipc_shm_ctrl: memory@0 {
reg = <0x0 0x1000>;
};
/* TX heap, user defined */
cpuapp_cpucell_ipc_shm_heap: memory@1000 {
reg = <0x1000 0x4000>;
};
/* RX heap, user defined */
cpucell_cpuapp_ipc_shm_heap: memory@5000 {
reg = <0x5000 0x4000>;
};
};
/* Shared memory ownership.
* TODO:
* remove these two after https://github.com/zephyrproject-rtos/zephyr/pull/72273
* and let cpuapp_cpucell_ram0x_region use the `access` binding to describe
* the shared memory ownership.
*/
cpuapp_cpucell_ipc_shm: memory@2 {
compatible = "nordic,owned-memory";
reg = <0x2f0d0000 DT_SIZE_K(36)>;
owner-id = <2>;
perm-read;
perm-write;
status = "disabled";
};
cpucell_cpuapp_ipc_shm: memory@4 {
compatible = "nordic,owned-memory";
reg = <0x2f0d0000 DT_SIZE_K(36)>;
owner-id = <4>;
perm-read;
perm-write;
status = "disabled";
};
shared_ram20_region: memory@2f88f000 {
reg = <0x2f88f000 DT_SIZE_K(4)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2f88f000 0x1000>;
cpuapp_cpusys_ipc_shm: memory@ce0 {
reg = <0xce0 0x80>;
};
cpusys_cpuapp_ipc_shm: memory@d60 {
reg = <0xd60 0x80>;
};
cpurad_cpusys_ipc_shm: memory@e00 {
reg = <0xe00 0x80>;
};
cpusys_cpurad_ipc_shm: memory@e80 {
reg = <0xe80 0x80>;
};
};
ram21_region: memory@2f890000 {
compatible = "nordic,owned-memory";
status = "disabled";
reg = <0x2f890000 DT_SIZE_K(32)>;
perm-read;
perm-write;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2f890000 0x8000>;
dma_fast_region: memory@4000 {
compatible = "zephyr,memory-region";
reg = <0x4000 DT_SIZE_K(16)>;
status = "disabled";
#memory-region-cells = <0>;
zephyr,memory-region = "DMA_RAM21";
zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>;
};
};
cpuppr_ram3x_region: memory@2fc00000 {
compatible = "nordic,owned-memory";
reg = <0x2fc00000 DT_SIZE_K(24)>;
status = "disabled";
perm-read;
perm-write;
perm-execute;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2fc00000 0x6000>;
cpuppr_code_data: memory@0 {
reg = <0x0 DT_SIZE_K(22)>;
};
cpuapp_cpuppr_ipc_shm: memory@5800 {
reg = <0x5800 DT_SIZE_K(1)>;
};
cpuppr_cpuapp_ipc_shm: memory@5c00 {
reg = <0x5c00 DT_SIZE_K(1)>;
};
};
shared_ram3x_region: memory@2fc06000 {
compatible = "nordic,owned-memory";
reg = <0x2fc06000 DT_SIZE_K(8)>;
status = "disabled";
perm-read;
perm-write;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2fc06000 0x4000>;
cpuapp_dma_region: memory@0 {
compatible = "zephyr,memory-region";
reg = <0x0 DT_SIZE_K(4)>;
status = "disabled";
#memory-region-cells = <0>;
zephyr,memory-region = "DMA_RAM3x_APP";
zephyr,memory-attr = <( DT_MEM_DMA )>;
};
cpurad_dma_region: memory@1000 {
compatible = "zephyr,memory-region";
reg = <0x1000 0x80>;
status = "disabled";
#memory-region-cells = <0>;
zephyr,memory-region = "DMA_RAM3x_RAD";
zephyr,memory-attr = <( DT_MEM_DMA )>;
};
};
};
};
&mram1x {
cpurad_rx_partitions: cpurad-rx-partitions {
compatible = "nordic,owned-partitions", "fixed-partitions";
status = "disabled";
perm-read;
perm-execute;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
cpurad_slot0_partition: partition@402000 {
reg = <0x402000 DT_SIZE_K(256)>;
};
};
cpuapp_rx_partitions: cpuapp-rx-partitions {
compatible = "nordic,owned-partitions", "fixed-partitions";
status = "disabled";
perm-read;
perm-execute;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
cpuapp_slot0_partition: partition@442000 {
reg = <0x442000 DT_SIZE_K(1024)>;
};
cpuppr_code_partition: partition@542000 {
reg = <0x542000 DT_SIZE_K(64)>;
};
};
cpuapp_rw_partitions: cpuapp-rw-partitions {
compatible = "nordic,owned-partitions", "fixed-partitions";
status = "disabled";
perm-read;
perm-write;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
dfu_partition: partition@600000 {
reg = <0x600000 DT_SIZE_K(512)>;
};
storage_partition: partition@680000 {
reg = <0x680000 DT_SIZE_K(24)>;
};
};
};

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boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-pinctrl.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&pinctrl {
/omit-if-no-ref/ uart135_default: uart135_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 4)>,
<NRF_PSEL(UART_RTS, 1, 0)>;
};
group3 {
bias-pull-up;
psels = <NRF_PSEL(UART_RX, 1, 5)>,
<NRF_PSEL(UART_CTS, 1, 6)>;
};
};
/omit-if-no-ref/ uart135_sleep: uart135_sleep {
group1 {
low-power-enable;
psels = <NRF_PSEL(UART_TX, 1, 4)>,
<NRF_PSEL(UART_RX, 1, 5)>,
<NRF_PSEL(UART_RTS, 1, 0)>,
<NRF_PSEL(UART_CTS, 1, 6)>;
};
};
/omit-if-no-ref/ uart136_default: uart136_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 4)>,
<NRF_PSEL(UART_RTS, 0, 0)>;
};
group3 {
bias-pull-up;
psels = <NRF_PSEL(UART_RX, 0, 5)>,
<NRF_PSEL(UART_CTS, 0, 6)>;
};
};
/omit-if-no-ref/ uart136_sleep: uart136_sleep {
group1 {
low-power-enable;
psels = <NRF_PSEL(UART_TX, 0, 4)>,
<NRF_PSEL(UART_RX, 0, 5)>,
<NRF_PSEL(UART_RTS, 0, 0)>,
<NRF_PSEL(UART_CTS, 0, 6)>;
};
};
/omit-if-no-ref/ exmif_default: exmif_default {
group1 {
psels = <NRF_PSEL(EXMIF_CK, 6, 0)>,
<NRF_PSEL(EXMIF_DQ0, 6, 7)>,
<NRF_PSEL(EXMIF_DQ1, 6, 5)>;
nordic,drive-mode = <NRF_DRIVE_H0H1>;
};
};
/omit-if-no-ref/ can120_default: can120_default {
group1 {
psels = <NRF_PSEL(CAN_RX, 9, 4)>,
<NRF_PSEL(CAN_TX, 9, 5)>;
};
};
/omit-if-no-ref/ pwm130_default: pwm130_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 9, 2)>;
};
};
/omit-if-no-ref/ pwm130_sleep: pwm130_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 9, 2)>;
low-power-enable;
};
};
};

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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf9280_cpuapp.dtsi>
#include "nrf9280pdk_nrf9280-memory_map.dtsi"
#include "nrf9280pdk_nrf9280-ipc_conf.dtsi"
#include "nrf9280pdk_nrf9280-pinctrl.dtsi"
/delete-node/ &cpurad_cpusys_ipc;
/delete-node/ &cpusec_cpurad_ipc;
/ {
compatible = "nordic,nrf9280pdk_nrf9280-cpuapp";
model = "Nordic nRF9280 DK nRF9280 Application MCU";
chosen {
zephyr,console = &uart136;
zephyr,code-partition = &cpuapp_slot0_partition;
zephyr,flash = &mram1x;
zephyr,sram = &cpuapp_data;
zephyr,shell-uart = &uart136;
zephyr,ieee802154 = &cpuapp_ieee802154;
zephyr,bt-hci = &bt_hci_ipc0;
nordic,802154-spinel-ipc = &ipc0;
zephyr,canbus = &can120;
};
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
led3 = &led3;
resetinfo = &cpuapp_resetinfo;
pwm-led0 = &pwm_led0;
sw0 = &button0;
sw1 = &button1;
sw2 = &button2;
sw3 = &button3;
ipc-to-cpusys = &cpuapp_cpusys_ipc;
watchdog0 = &wdt010;
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 0";
zephyr,code = <INPUT_KEY_0>;
};
button1: button_1 {
gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 1";
zephyr,code = <INPUT_KEY_1>;
};
button2: button_2 {
gpios = <&gpio0 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 2";
zephyr,code = <INPUT_KEY_2>;
};
button3: button_3 {
gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 3";
zephyr,code = <INPUT_KEY_3>;
};
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
label = "Green LED 0";
};
led1: led_1 {
gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
label = "Green LED 1";
};
led2: led_2 {
gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
label = "Green LED 2";
};
led3: led_3 {
gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
label = "Green LED 3";
};
};
pwmleds {
compatible = "pwm-leds";
/*
* LEDs are connected to GPIO Port 9 - pins 2-5. There is no valid hardware
* configuration to pass PWM signal on pins 0 and 1. First valid config is P9.2.
* Signal on PWM130's channel 0 can be passed directly on GPIO Port 9 pin 2.
*/
pwm_led0: pwm_led_0 {
pwms = <&pwm130 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
};
&cpuapp_ram0x_region {
status = "okay";
};
&cpuapp_cpurad_ram0x_region {
status = "okay";
};
&cpuapp_cpucell_ipc_shm {
status = "okay";
};
&cpucell_cpuapp_ipc_shm {
status = "okay";
};
&shared_ram3x_region {
status = "okay";
};
&ram21_region {
status = "okay";
};
&cpuapp_bellboard {
status = "okay";
interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>;
interrupt-names = "irq0";
/* The following bells on this bellboard are rang by these cores
* - Bell 0: cpusec
* - Bell 6: cpusys
* - Bell 13: cpuppr
* - Bell 18: cpurad
* - Bells 24, 25, 29, 31: cpucell
*/
nordic,interrupt-mapping = <0xA3042041 0>;
};
&cpurad_bellboard {
status = "okay";
};
&cpucell_bellboard {
status = "okay";
};
&cpusys_vevif {
status = "okay";
};
&cpusec_cpuapp_ipc {
mbox-names = "tx", "rx";
tx-region = <&cpuapp_cpusec_ipc_shm>;
rx-region = <&cpusec_cpuapp_ipc_shm>;
};
ipc0: &cpuapp_cpurad_ipc {
status = "okay";
mbox-names = "rx", "tx";
tx-region = <&cpuapp_cpurad_ipc_shm>;
rx-region = <&cpurad_cpuapp_ipc_shm>;
tx-blocks = <32>;
rx-blocks = <32>;
bt_hci_ipc0: bt_hci_ipc0 {
compatible = "zephyr,bt-hci-ipc";
status = "okay";
};
};
&cpuapp_cpusys_ipc {
status = "okay";
mbox-names = "rx", "tx";
tx-region = <&cpuapp_cpusys_ipc_shm>;
rx-region = <&cpusys_cpuapp_ipc_shm>;
};
&cpuapp_cpuppr_ipc {
mbox-names = "rx", "tx";
tx-region = <&cpuapp_cpuppr_ipc_shm>;
rx-region = <&cpuppr_cpuapp_ipc_shm>;
};
&cpuapp_dma_region {
status = "okay";
};
&dma_fast_region {
status = "okay";
};
&cpuapp_rx_partitions {
status = "okay";
};
&cpuapp_rw_partitions {
status = "okay";
};
&cpuppr_vpr {
execution-memory = <&cpuppr_code_data>;
source-memory = <&cpuppr_code_partition>;
};
&gpiote130 {
status = "okay";
owned-channels = <0 1 2 3 4 5 6 7>;
};
&gpio0 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpio9 {
status = "okay";
};
&grtc {
status = "okay";
child-owned-channels = <5 6>;
nonsecure-channels = <5 6>;
owned-channels = <4 5 6>;
};
&uart135 {
current-speed = <115200>;
pinctrl-0 = <&uart135_default>;
pinctrl-1 = <&uart135_sleep>;
pinctrl-names = "default", "sleep";
};
&uart136 {
status = "okay";
memory-regions = <&cpuapp_dma_region>;
current-speed = <115200>;
pinctrl-0 = <&uart136_default>;
pinctrl-1 = <&uart136_sleep>;
pinctrl-names = "default", "sleep";
hw-flow-control;
};
&gpio6 {
status = "okay";
};
&exmif {
cs-gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&exmif_default>;
pinctrl-names = "default";
status = "okay";
mx25uw63: mx25uw6345g@0 {
compatible = "jedec,spi-nor";
status = "disabled";
reg = <0>;
spi-max-frequency = <DT_FREQ_M(48)>;
jedec-id = [c2 84 37];
sfdp-bfp = [
e5 20 8a ff ff ff ff 03 00 ff 00 ff 00 ff 00 ff
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 10 d8
00 ff 00 ff 87 79 01 00 84 12 00 c4 cc 04 67 46
30 b0 30 b0 f4 bd d5 5c 00 00 00 ff 10 10 00 20
00 00 00 00 00 00 7c 23 48 00 00 00 00 00 88 88
];
size = <67108864>;
has-dpd;
t-enter-dpd = <10000>;
t-exit-dpd = <30000>;
};
};
&cpuapp_ieee802154 {
status = "okay";
};
zephyr_udc0: &usbhs {
status = "okay";
};
&canpll {
status = "okay";
};
&can120 {
status = "okay";
pinctrl-0 = <&can120_default>;
pinctrl-names = "default";
};
&pwm130 {
status = "okay";
pinctrl-0 = <&pwm130_default>;
pinctrl-1 = <&pwm130_sleep>;
pinctrl-names = "default", "sleep";
memory-regions = <&cpuapp_dma_region>;
};
&adc {
memory-regions = <&cpuapp_dma_region>;
status = "okay";
};

24
boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.yaml Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf9280pdk/nrf9280/cpuapp
name: nRF9280-DK-nRF9280-Application
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
sysbuild: true
ram: 512
flash: 1024
supported:
- adc
- can
- counter
- gpio
- i2c
- pwm
- spi
- watchdog
- usbd

28
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_USE_DT_CODE_PARTITION=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# MPU-based null-pointer dereferencing detection cannot be applied
# as the (0x0 - 0x400) region is unmapped for this target.
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
# Enable cache
CONFIG_CACHE_MANAGEMENT=y
CONFIG_EXTERNAL_CACHE=y
# Enable GPIO
CONFIG_GPIO=y

60
boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.dts Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf9280_cpuppr.dtsi>
#include "nrf9280pdk_nrf9280-memory_map.dtsi"
#include "nrf9280pdk_nrf9280-ipc_conf.dtsi"
#include "nrf9280pdk_nrf9280-pinctrl.dtsi"
/delete-node/ &cpuapp_cpurad_ipc;
/delete-node/ &cpuapp_cpusys_ipc;
/delete-node/ &cpurad_cpusys_ipc;
/delete-node/ &cpusec_cpuapp_ipc;
/delete-node/ &cpusec_cpurad_ipc;
/ {
compatible = "nordic,nrf9280pdk_nrf9280-cpuppr";
model = "Nordic nRF9280 DK nRF9280 Peripheral Processor MCU";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &uart135;
zephyr,code-partition = &cpuppr_code_partition;
zephyr,flash = &mram1x;
zephyr,sram = &cpuppr_code_data;
zephyr,shell-uart = &uart135;
};
};
&cpuapp_cpuppr_ipc {
mbox-names = "tx", "rx";
tx-region = <&cpuppr_cpuapp_ipc_shm>;
rx-region = <&cpuapp_cpuppr_ipc_shm>;
};
&grtc {
status = "okay";
owned-channels = <5>;
};
&uart135 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart135_default>;
pinctrl-1 = <&uart135_sleep>;
pinctrl-names = "default", "sleep";
hw-flow-control;
};
&uart136 {
current-speed = <115200>;
pinctrl-0 = <&uart136_default>;
pinctrl-1 = <&uart136_sleep>;
pinctrl-names = "default", "sleep";
};

18
boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.yaml Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf9280pdk/nrf9280/cpuppr
name: nRF9280-DK-nRF9280-PPR
type: mcu
arch: riscv
toolchain:
- zephyr
sysbuild: true
ram: 22
flash: 22
supported:
- counter
- gpio
- i2c
- pwm
- spi

14
boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_defconfig Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_USE_DT_CODE_PARTITION=y
# Execute from RAM
CONFIG_XIP=n

7
boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.dts Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "nrf9280pdk_nrf9280_cpuppr.dts"

14
boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip.yaml Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf9280pdk/nrf9280/cpuppr/xip
name: nRF9280-DK-nRF9280-PPR (MRAM XIP)
type: mcu
arch: riscv
toolchain:
- zephyr
sysbuild: true
ram: 22
flash: 64
supported:
- gpio

13
boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr_xip_defconfig Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_USE_DT_CODE_PARTITION=y
CONFIG_XIP=y

119
boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf9280_cpurad.dtsi>
#include "nrf9280pdk_nrf9280-memory_map.dtsi"
#include "nrf9280pdk_nrf9280-ipc_conf.dtsi"
#include "nrf9280pdk_nrf9280-pinctrl.dtsi"
/delete-node/ &cpuapp_cpuppr_ipc;
/delete-node/ &cpuapp_cpusys_ipc;
/delete-node/ &cpusec_cpuapp_ipc;
/ {
compatible = "nordic,nrf9280pdk_nrf9280-cpurad";
model = "Nordic nRF9280 DK nRF9280 Radio MCU";
chosen {
zephyr,console = &uart135;
zephyr,code-partition = &cpurad_slot0_partition;
zephyr,flash = &mram1x;
zephyr,sram = &cpurad_ram0;
zephyr,shell-uart = &uart135;
zephyr,ieee802154 = &cpurad_ieee802154;
zephyr,bt-hci-ipc = &ipc0;
nordic,802154-spinel-ipc = &ipc0;
};
aliases {
ipc-to-cpusys = &cpurad_cpusys_ipc;
resetinfo = &cpurad_resetinfo;
};
};
&shared_ram3x_region {
status = "okay";
};
&cpuapp_cpurad_ram0x_region {
status = "okay";
};
&cpurad_bellboard {
status = "okay";
interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>;
interrupt-names = "irq0";
/* The following bells on this bellboard are rang by these cores
* - Bell 0: cpusec
* - Bell 6: cpusys
* - Bell 12: cpuapp
*/
nordic,interrupt-mapping = <0x00001041 0>;
};
&cpuapp_bellboard {
status = "okay";
};
&cpusys_vevif {
status = "okay";
};
&cpusec_cpurad_ipc {
mbox-names = "tx", "rx";
tx-region = <&cpurad_cpusec_ipc_shm>;
rx-region = <&cpusec_cpurad_ipc_shm>;
};
ipc0: &cpuapp_cpurad_ipc {
status = "okay";
mbox-names = "tx", "rx";
tx-region = <&cpurad_cpuapp_ipc_shm>;
rx-region = <&cpuapp_cpurad_ipc_shm>;
tx-blocks = <32>;
rx-blocks = <32>;
};
&cpurad_cpusys_ipc {
status = "okay";
mbox-names = "rx", "tx";
tx-region = <&cpurad_cpusys_ipc_shm>;
rx-region = <&cpusys_cpurad_ipc_shm>;
};
&cpurad_dma_region {
status = "okay";
};
&cpurad_rx_partitions {
status = "okay";
};
&grtc {
status = "okay";
};
&uart135 {
status = "okay";
memory-regions = <&cpurad_dma_region>;
current-speed = <115200>;
pinctrl-0 = <&uart135_default>;
pinctrl-1 = <&uart135_sleep>;
pinctrl-names = "default", "sleep";
hw-flow-control;
};
&uart136 {
current-speed = <115200>;
pinctrl-0 = <&uart136_default>;
pinctrl-1 = <&uart136_sleep>;
pinctrl-names = "default", "sleep";
};
&cpurad_ieee802154 {
status = "okay";
};

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boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.yaml Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf9280pdk/nrf9280/cpurad
name: nRF9280-DK-nRF9280-Radio
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
sysbuild: true
ram: 32
flash: 256
supported:
- counter
- gpio
- pwm
- spi

25
boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad_defconfig Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_USE_DT_CODE_PARTITION=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# MPU-based null-pointer dereferencing detection cannot be applied
# as the (0x0 - 0x400) region is unmapped for this target.
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
# Enable cache
CONFIG_CACHE_MANAGEMENT=y
CONFIG_EXTERNAL_CACHE=y

41
boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript Normal file
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// Debug Halting Control and Status Register
__constant U32 _DHCSR_ADDR = 0xE000EDF0;
__constant U32 _DHCSR_DBGKEY = (0xA05F << 16);
__constant U32 _DHCSR_C_DEBUGEN = (1 << 0);
__constant U32 _DHCSR_C_HALT = (1 << 1);
// Debug Exception and Monitor Control Register
__constant U32 _DEMCR_ADDR = 0xE000EDFC;
__constant U32 _DEMCR_VC_CORERESET = (1 << 0);
__constant U32 _DEMCR_TRCENA = (1 << 24);
// CPU wait enable register
__constant U32 _CPUCONF_CPUWAIT_ADDR = 0x5201150C;
int ResetTarget(void) {
// ADAC reset
JLINK_CORESIGHT_WriteDP(2, 0x04000010);
JLINK_CORESIGHT_WriteAP(0, 0xA3030000);
JLINK_CORESIGHT_WriteAP(0, 0x00000004);
JLINK_CORESIGHT_WriteAP(0, 0x01020000);
JLINK_SYS_Sleep(100);
JLINK_CORESIGHT_ReadAP(2);
JLINK_CORESIGHT_ReadAP(2);
JLINK_CORESIGHT_ReadAP(2);
JLINK_CORESIGHT_ReadAP(2);
// Halt the CPU
JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN));
// Set vector catch on reset (to halt the CPU immediately after reset)
JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA));
// Disable CPU wait
JLINK_MEM_WriteU32(_CPUCONF_CPUWAIT_ADDR, 0);
// Clear vector catch stuff
JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA);
return 0;
}

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// Debug Halting Control and Status Register
__constant U32 _DHCSR_ADDR = 0xE000EDF0;
__constant U32 _DHCSR_DBGKEY = (0xA05F << 16);
__constant U32 _DHCSR_C_DEBUGEN = (1 << 0);
__constant U32 _DHCSR_C_HALT = (1 << 1);
// Debug Exception and Monitor Control Register
__constant U32 _DEMCR_ADDR = 0xE000EDFC;
__constant U32 _DEMCR_VC_CORERESET = (1 << 0);
__constant U32 _DEMCR_TRCENA = (1 << 24);
// CPU wait enable register
__constant U32 _CPUCONF_CPUWAIT_ADDR = 0x5301150C;
int ConfigTargetSettings(void) {
JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP");
CORESIGHT_IndexAHBAPToUse = 1;
return 0;
}
int ResetTarget(void) {
// ADAC reset
JLINK_CORESIGHT_WriteDP(2, 0x04000010);
JLINK_CORESIGHT_WriteAP(0, 0xA3030000);
JLINK_CORESIGHT_WriteAP(0, 0x00000004);
JLINK_CORESIGHT_WriteAP(0, 0x01030000);
JLINK_SYS_Sleep(100);
JLINK_CORESIGHT_ReadAP(2);
JLINK_CORESIGHT_ReadAP(2);
JLINK_CORESIGHT_ReadAP(2);
JLINK_CORESIGHT_ReadAP(2);
// Halt the CPU
JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN));
// Set vector catch on reset (to halt the CPU immediately after reset)
JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA));
// Disable CPU wait
JLINK_MEM_WriteU32(_CPUCONF_CPUWAIT_ADDR, 0);
// Clear vector catch stuff
JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA);
return 0;
}