soc: espressif: esp32: Allow DRAM1 to use for .noinit

Add config to relocate the .noinit section to DRAM1 region.
Remove unused config.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit is contained in:
Marek Matej 2025-02-19 14:22:39 +01:00 committed by Benjamin Cabé
commit f10e7b8395
4 changed files with 27 additions and 25 deletions

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@ -1,11 +1,7 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
CONFIG_ESP_HEAP_MEM_POOL_REGION_1_SIZE=0
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_REGULATOR=y CONFIG_REGULATOR=y
CONFIG_CONSOLE=y CONFIG_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y

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@ -20,16 +20,13 @@ config ESP32_BT_RESERVE_DRAM
default 0xdb5c if BT default 0xdb5c if BT
default 0 default 0
config ESP_HEAP_MEM_POOL_REGION_1_SIZE config ESP32_REGION_1_NOINIT
int "Internal DRAM region 1 mempool size" bool "Use DRAM region 1 to spill noinit section"
default 0 if MCUBOOT default n
default 1024 if SOC_ESP32_PROCPU
default 49152
help help
ESP32 has two banks of size 192K and 128K which can be used ESP32 has two banks of size 192K and 128K which can be used
as DRAM, system heap allocates area from region 0. as DRAM. Enabling this option would allocate .noinit sections
This configuration can be used to add memory from region 1 in the DRAM region 1, instead of default region 0.
to heap and can be allocated using k_malloc.
config ESP32_DEEP_SLEEP_WAKEUP_DELAY config ESP32_DEEP_SLEEP_WAKEUP_DELAY
int "Extra delay in deep sleep wake stub (in us)" int "Extra delay in deep sleep wake stub (in us)"

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@ -13,16 +13,16 @@
#include "memory.h" #include "memory.h"
/* User available SRAM memory segments */ /* User available SRAM memory segments */
procpu_iram_end = USER_IRAM_END - APPCPU_SRAM_SIZE; procpu_iram0_end = USER_IRAM_END - APPCPU_SRAM_SIZE;
procpu_iram_org = SRAM0_IRAM_START + SRAM0_CACHE_SIZE; procpu_iram0_org = SRAM0_IRAM_START + SRAM0_CACHE_SIZE;
procpu_iram_len = procpu_iram_end - procpu_iram_org; procpu_iram0_len = procpu_iram0_end - procpu_iram0_org;
procpu_dram_end = SRAM2_DRAM_END; procpu_dram0_end = SRAM2_DRAM_END;
procpu_dram_org = SRAM2_DRAM_USER_START + CONFIG_ESP32_BT_RESERVE_DRAM; procpu_dram0_org = SRAM2_DRAM_USER_START + CONFIG_ESP32_BT_RESERVE_DRAM;
procpu_dram_len = SRAM2_DRAM_USER_SIZE - CONFIG_ESP32_BT_RESERVE_DRAM; procpu_dram0_len = SRAM2_DRAM_USER_SIZE - CONFIG_ESP32_BT_RESERVE_DRAM;
user_dram_2_seg_org = SRAM1_DRAM_USER_START; procpu_dram1_org = SRAM1_DRAM_USER_START;
user_dram_2_seg_len = SRAM1_USER_SIZE; procpu_dram1_len = SRAM1_DRAM_USER_SIZE;
procpu_irom_org = ICACHE0_START; procpu_irom_org = ICACHE0_START;
procpu_irom_len = ICACHE0_SIZE; procpu_irom_len = ICACHE0_SIZE;
@ -40,7 +40,14 @@ procpu_ext_ram_len = DCACHE1_SIZE;
#define IRAM_REGION iram0_0_seg #define IRAM_REGION iram0_0_seg
#define DRAM_REGION dram0_0_seg #define DRAM_REGION dram0_0_seg
#define RAMABLE_REGION dram0_0_seg #define RAMABLE_REGION dram0_0_seg
#define ROMABLE_REGION FLASH
#ifndef CONFIG_ESP32_REGION_1_NOINIT
#define RAMABLE_REGION_2 dram0_0_seg
#else
#define RAMABLE_REGION_2 dram1_0_seg
#endif
#define ROMABLE_REGION FLASH
#undef GROUP_DATA_LINK_IN #undef GROUP_DATA_LINK_IN
#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion #define GROUP_DATA_LINK_IN(vregion, lregion) > vregion AT > lregion
@ -73,8 +80,9 @@ MEMORY
FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100 FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100
#endif /* CONFIG_BOOTLOADER_MCUBOOT */ #endif /* CONFIG_BOOTLOADER_MCUBOOT */
iram0_0_seg(RX): org = procpu_iram_org, len = procpu_iram_len iram0_0_seg(RX): org = procpu_iram0_org, len = procpu_iram0_len
dram0_0_seg(RW): org = procpu_dram_org, len = procpu_dram_len dram0_0_seg(RW): org = procpu_dram0_org, len = procpu_dram0_len
dram1_0_seg(RW): org = procpu_dram1_org, len = procpu_dram1_len
irom0_0_seg(RX): org = procpu_irom_org, len = procpu_irom_len irom0_0_seg(RX): org = procpu_irom_org, len = procpu_irom_len
drom0_0_seg(R): org = procpu_drom_org, len = procpu_drom_len drom0_0_seg(R): org = procpu_drom_org, len = procpu_drom_len
@ -802,7 +810,7 @@ SECTIONS
#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */ #endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */
__dram_noinit_end = ABSOLUTE(.); __dram_noinit_end = ABSOLUTE(.);
. = ALIGN (4); . = ALIGN (4);
} GROUP_LINK_IN(RAMABLE_REGION) } GROUP_LINK_IN(RAMABLE_REGION_2)
/* Provide total SRAM usage, including IRAM and DRAM */ /* Provide total SRAM usage, including IRAM and DRAM */
_image_ram_start = _dram_data_start; _image_ram_start = _dram_data_start;
@ -815,6 +823,7 @@ SECTIONS
/* --- SPIRAM BEGIN --- */ /* --- SPIRAM BEGIN --- */
/* The SPIRAM section needs to be spilled before the dram0.noinit */
#ifdef CONFIG_ESP_SPIRAM #ifdef CONFIG_ESP_SPIRAM
.ext_ram (NOLOAD): .ext_ram (NOLOAD):
{ {

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@ -16,7 +16,7 @@
#define SRAM1_DRAM_END (SRAM1_DRAM_START + SRAM1_SIZE) #define SRAM1_DRAM_END (SRAM1_DRAM_START + SRAM1_SIZE)
#define SRAM1_RESERVED_SIZE 0x8000 #define SRAM1_RESERVED_SIZE 0x8000
#define SRAM1_DRAM_USER_START (SRAM1_DRAM_START + SRAM1_RESERVED_SIZE) #define SRAM1_DRAM_USER_START (SRAM1_DRAM_START + SRAM1_RESERVED_SIZE)
#define SRAM1_USER_SIZE (0x40000000 - SRAM1_DRAM_USER_START) #define SRAM1_DRAM_USER_SIZE (0x40000000 - SRAM1_DRAM_USER_START)
/* SRAM2 (200kB) data memory */ /* SRAM2 (200kB) data memory */
#define SRAM2_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram2)) #define SRAM2_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram2))