boards/socs: Rename folders to have proper vendor prefix in

Replaces inaccurate or wrong vendor prefixes in board and soc
folder names with those from thr vendor prefix file

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

soc/snps/arc_iot/CMakeLists.txt

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata -mmpy-option=6)
+zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all)
+
+zephyr_sources(
+  soc.c
+  sysconf.c
+  )
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/snps/arc_iot/Kconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ARC_IOT
+	select ARC
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU

soc/snps/arc_iot/Kconfig.defconfig

@@ -0,0 +1,34 @@
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_ARC_IOT
+
+config CPU_EM4_FPUS
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config ARC_MPU_VER
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 95
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 144000000
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+endif # ARC_IOT

soc/snps/arc_iot/Kconfig.soc

@@ -0,0 +1,11 @@
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ARC_IOT
+	bool
+	help
+	  Synopsys ARC IoT SoC
+
+config SOC
+	default "arc_iot" if SOC_ARC_IOT

soc/snps/arc_iot/linker.ld

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the Synopsys ARC IoT Development Kit
+ */
+
+#include <zephyr/devicetree.h>
+
+/*
+ * SRAM base address and size
+ *
+ */
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
+    (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
+#define SRAM_START		DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
+#define SRAM_SIZE		DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
+#endif
+
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_flash), reg) && \
+    (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
+#define FLASH_START		DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
+#define FLASH_SIZE		DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
+#endif
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#if DT_NODE_HAS_PROP(DT_INST(0, arc_iccm), reg) && \
+    (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
+#define ICCM_START		DT_REG_ADDR(DT_INST(0, arc_iccm))
+#define ICCM_SIZE		DT_REG_SIZE(DT_INST(0, arc_iccm))
+#endif
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+#if DT_NODE_HAS_PROP(DT_INST(0, arc_dccm), reg) && \
+    (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
+#define DCCM_START		DT_REG_ADDR(DT_INST(0, arc_dccm))
+#define DCCM_SIZE		DT_REG_SIZE(DT_INST(0, arc_dccm))
+#endif
+
+#include <zephyr/arch/arc/v2/xy_mem.ld>
+#include <zephyr/arch/arc/v2/linker.ld>

soc/snps/arc_iot/soc.c

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * This module provides routines to initialize and support soc-level hardware
+ * for the IoT Development Kit board.
+ *
+ */
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include "sysconf.h"
+
+#define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
+
+static int arc_iot_init(void)
+{
+
+	if (arc_iot_pll_fout_config(CPU_FREQ / 1000000) < 0) {
+		return -1;
+	}
+
+	return 0;
+}
+
+SYS_INIT(arc_iot_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/snps/arc_iot/soc.yml

@@ -0,0 +1,4 @@
+series:
+- name: arc_iot
+  socs:
+  - name: arc_iot

soc/snps/arc_iot/sysconf.c

@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include "sysconf.h"
+
+/* default system clock */
+#define SYSCLK_DEFAULT_IOSC_HZ			MHZ(16)
+
+#define PLL_CLK_IN	(SYSCLK_DEFAULT_IOSC_HZ / 1000000)  /* PLL clock in */
+
+
+#define sysconf_reg_ptr ((sysconf_reg_t *)(DT_REG_ADDR(DT_NODELABEL(sysconf))))
+
+
+typedef struct pll_conf {
+	uint32_t fout;
+	uint32_t pll;
+} pll_conf_t;
+
+#define PLL_CONF_VAL(n, m, od) \
+	(((n) << PLLCON_BIT_OFFSET_N) | \
+	((m) << (PLLCON_BIT_OFFSET_M)) | \
+	((od) << PLLCON_BIT_OFFSET_OD))
+
+
+/* the following configuration is based on Fin = 16 Mhz */
+static const pll_conf_t pll_configuration[] = {
+	{100, PLL_CONF_VAL(1, 25, 2)},  /* 100 Mhz */
+	{50,  PLL_CONF_VAL(1, 25, 3)},  /* 50 Mhz */
+	{150, PLL_CONF_VAL(4, 75, 1)},  /* 150 Mhz */
+	{75,  PLL_CONF_VAL(4, 75, 2)},  /* 75 Mhz */
+	{25,  PLL_CONF_VAL(2, 25, 3)},  /* 25 Mhz */
+	{72,  PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */
+	{144, PLL_CONF_VAL(8, 144, 1)}, /* 144 Mhz */
+};
+
+
+/**
+ * PLL Fout = Fin * M/ (N *n NO)
+ *
+ * Fref = Fin / N; Fvco = Fref * M Fout = Fvco / NO
+ *
+ *  N = input divider value (1, 2, 3 … 15)
+ *  M = feedback divider value (4, 5, 6 … 16383)
+ *  NO = output divider value (1, 2, 4, or 8)
+ *
+ *  1 Mhz <= Fref <= 50 Mhz
+ *  200 Mhz <= Fvco <= 400 Mhz
+ *
+ */
+void arc_iot_pll_conf_reg(uint32_t val)
+{
+
+	sysconf_reg_ptr->CLKSEL = CLKSEL_EXT_16M;
+	/* 0x52000000 is not described in spec. */
+	sysconf_reg_ptr->PLLCON = val | (0x52000000);
+
+	sysconf_reg_ptr->PLLCON = val | (1 << PLLCON_BIT_OFFSET_PLLRST);
+	sysconf_reg_ptr->PLLCON = val & (~(1 << PLLCON_BIT_OFFSET_PLLRST));
+
+	while (!(sysconf_reg_ptr->PLLSTAT & (1 << PLLSTAT_BIT_OFFSET_PLLSTB))) {
+		;
+	}
+
+	sysconf_reg_ptr->CLKSEL = CLKSEL_PLL;
+	/* from AHB_CLK_DIVIDER, not from DVFSS&PMC */
+	sysconf_reg_ptr->AHBCLKDIV_SEL |= 1;
+	/* AHB clk divisor = 1 */
+	sysconf_reg_ptr->AHBCLKDIV = 0x1;
+}
+
+int32_t arc_iot_pll_fout_config(uint32_t freq)
+{
+	uint32_t i;
+
+	if (freq == PLL_CLK_IN) {
+		sysconf_reg_ptr->CLKSEL = CLKSEL_EXT_16M;
+	}
+
+	for (i = 0U; i < ARRAY_SIZE(pll_configuration); i++) {
+		if (pll_configuration[i].fout == freq) {
+			break;
+		}
+	}
+
+	if (i >= ARRAY_SIZE(pll_configuration)) {
+		return -1;
+	}
+
+	/* config eflash clk, must be < 100 Mhz */
+	if (freq > 100) {
+		arc_iot_eflash_clk_div(2);
+	} else {
+		arc_iot_eflash_clk_div(1);
+	}
+
+	arc_iot_pll_conf_reg(pll_configuration[i].pll);
+
+	return 0;
+}
+
+void arc_iot_ahb_clk_divisor(uint8_t div)
+{
+	sysconf_reg_ptr->AHBCLKDIV = div;
+}
+
+void arc_iot_ahb_clk_enable(uint8_t dev)
+{
+	if (dev > AHBCLKEN_BIT_SDIO) {
+		return;
+	}
+
+	sysconf_reg_ptr->AHBCLKEN |= (1 << dev);
+}
+
+void arc_iot_ahb_clk_disable(uint8_t dev)
+{
+	if (dev > AHBCLKEN_BIT_SDIO) {
+		return;
+	}
+
+	sysconf_reg_ptr->AHBCLKEN &= (~(1 << dev));
+}
+
+void arc_iot_apb_clk_divisor(uint8_t div)
+{
+	sysconf_reg_ptr->APBCLKDIV = div;
+}
+
+void arc_iot_apb_clk_enable(uint8_t dev)
+{
+	if (dev > APBCLKEN_BIT_I3C) {
+		return;
+	}
+
+	sysconf_reg_ptr->APBCLKEN |= (1 << dev);
+}
+
+void arc_iot_apb_clk_disable(uint8_t dev)
+{
+	if (dev > APBCLKEN_BIT_I3C) {
+		return;
+	}
+
+	sysconf_reg_ptr->APBCLKEN &= (~(1 << dev));
+}
+
+void arc_iot_dio_clk_divisor(uint8_t div)
+{
+	sysconf_reg_ptr->SDIO_REFCLK_DIV;
+}
+
+void arc_iot_spi_master_clk_divisor(uint8_t id, uint8_t div)
+{
+	if (id == SPI_MASTER_0) {
+		sysconf_reg_ptr->SPI_MST_CLKDIV =
+		    (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xffffff00) | div;
+	} else if (id == SPI_MASTER_1) {
+		sysconf_reg_ptr->SPI_MST_CLKDIV =
+		    (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xffff00ff) | (div << 8);
+	} else if (id == SPI_MASTER_2) {
+		sysconf_reg_ptr->SPI_MST_CLKDIV =
+		    (sysconf_reg_ptr->SPI_MST_CLKDIV & 0xff00ffff) | (div << 16);
+	}
+}
+
+void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div)
+{
+	if (bank == GPIO8B_BANK0) {
+		sysconf_reg_ptr->GPIO8B_DBCLK_DIV =
+		    (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xffffff00) | div;
+	} else if (bank == GPIO8B_BANK1) {
+		sysconf_reg_ptr->GPIO8B_DBCLK_DIV =
+		    (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xffff00ff) | (div << 8);
+	} else if (bank == GPIO8B_BANK2) {
+		sysconf_reg_ptr->GPIO8B_DBCLK_DIV =
+		    (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0xff00ffff) | (div << 16);
+	} else if (bank == GPIO8B_BANK3) {
+		sysconf_reg_ptr->GPIO8B_DBCLK_DIV =
+		    (sysconf_reg_ptr->GPIO8B_DBCLK_DIV & 0x00ffffff) | (div << 24);
+	}
+}
+
+void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div)
+{
+	if (bank == GPIO4B_BANK0) {
+		sysconf_reg_ptr->GPIO4B_DBCLK_DIV =
+		    (sysconf_reg_ptr->GPIO4B_DBCLK_DIV & 0xffffff00) | div;
+	} else if (bank == GPIO4B_BANK1) {
+		sysconf_reg_ptr->GPIO4B_DBCLK_DIV =
+		    (sysconf_reg_ptr->GPIO4B_DBCLK_DIV & 0xffff00ff) | (div << 8);
+	} else if (bank == GPIO4B_BANK2) {
+		sysconf_reg_ptr->GPIO4B_DBCLK_DIV =
+		    (sysconf_reg_ptr->GPIO4B_DBCLK_DIV & 0xff00ffff) | (div << 16);
+	}
+}
+
+void arc_iot_i2s_tx_clk_div(uint8_t div)
+{
+	sysconf_reg_ptr->I2S_TX_SCLKDIV = div;
+}
+
+void arc_iot_i2s_rx_clk_div(uint8_t div)
+{
+	sysconf_reg_ptr->I2S_RX_SCLKDIV = div;
+}
+
+void arc_iot_i2s_rx_clk_sel(uint8_t sel)
+{
+	sysconf_reg_ptr->I2S_RX_SCLKSEL = sel;
+}
+
+void arc_iot_syscon_reset(void)
+{
+	sysconf_reg_ptr->RSTCON = 0x55AA6699;
+}
+
+uint32_t arc_iot_is_poweron_rst(void)
+{
+	if (sysconf_reg_ptr->RSTSTAT & SYS_RST_SOFTWARE_ON) {
+		return 0;
+	} else {
+		return 1;
+	}
+}
+
+void arc_iot_dvfs_clk_divisor(uint8_t level, uint8_t div)
+{
+	if (level == DVFS_PERF_LEVEL0) {
+		sysconf_reg_ptr->DVFS_CLKDIV =
+		    (sysconf_reg_ptr->DVFS_CLKDIV & 0xffffff00) | div;
+	} else if (level == DVFS_PERF_LEVEL1) {
+		sysconf_reg_ptr->DVFS_CLKDIV =
+		    (sysconf_reg_ptr->DVFS_CLKDIV & 0xffff00ff) | (div << 8);
+	} else if (level == DVFS_PERF_LEVEL2) {
+		sysconf_reg_ptr->DVFS_CLKDIV =
+		    (sysconf_reg_ptr->DVFS_CLKDIV & 0xff00ffff) | (div << 16);
+	} else if (level == DVFS_PERF_LEVEL3) {
+		sysconf_reg_ptr->DVFS_CLKDIV =
+		    (sysconf_reg_ptr->DVFS_CLKDIV & 0x00ffffff) | (div << 24);
+	}
+}
+
+void arc_iot_dvfs_vdd_config(uint8_t level, uint8_t val)
+{
+	val &= 0xf;
+
+	if (level == DVFS_PERF_LEVEL0) {
+		sysconf_reg_ptr->DVFS_VDDSET =
+		    (sysconf_reg_ptr->DVFS_VDDSET & 0xfffffff0) | val;
+	} else if (level == DVFS_PERF_LEVEL1) {
+		sysconf_reg_ptr->DVFS_VDDSET =
+		    (sysconf_reg_ptr->DVFS_VDDSET & 0xffffff0f) | (val << 4);
+	} else if (level == DVFS_PERF_LEVEL2) {
+		sysconf_reg_ptr->DVFS_VDDSET =
+		    (sysconf_reg_ptr->DVFS_VDDSET & 0xfffff0ff) | (val << 8);
+	} else if (level == DVFS_PERF_LEVEL3) {
+		sysconf_reg_ptr->DVFS_CLKDIV =
+		    (sysconf_reg_ptr->DVFS_CLKDIV & 0xffff0fff) | (val << 12);
+	}
+}
+
+void arc_iot_dvfs_vwtime_config(uint8_t time)
+{
+	sysconf_reg_ptr->DVFS_VWTIME = time;
+}
+
+void arc_iot_pmc_pwwtime_config(uint8_t time)
+{
+	sysconf_reg_ptr->PMC_PUWTIME = time;
+}
+
+void arc_iot_uart3_clk_divisor(uint8_t div)
+{
+	sysconf_reg_ptr->UART3SCLK_DIV = div;
+}
+
+void arc_iot_reset_powerdown_vector(uint32_t addr)
+{
+	sysconf_reg_ptr->RESET_PD_VECTOR = addr;
+}
+
+void arc_iot_pwm_timer_pause(uint32_t id, uint32_t pause)
+{
+	uint32_t val = sysconf_reg_ptr->TIMER_PAUSE;
+
+	if (id > PWM_TIMER5) {
+		return;
+	}
+
+	if (pause) {
+		val |= (1 << id);
+	} else {
+		val &= (~(1 << id));
+	}
+
+	sysconf_reg_ptr->TIMER_PAUSE = val;
+}
+
+void arc_iot_eflash_clk_div(uint8_t div)
+{
+	sysconf_reg_ptr->AHBCLKDIV |= (div << 8);
+}

soc/snps/arc_iot/sysconf.h

@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#ifndef _ARC_IOT_SYSCONF_H_
+#define _ARC_IOT_SYSCONF_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct sysconf_reg {
+	volatile uint32_t reserved1;	/* 0x0 */
+	volatile uint32_t AHBCLKDIV;	/* AHB clock divisor */
+	volatile uint32_t APBCLKDIV; 	/* APB clock divisor */
+	volatile uint32_t APBCLKEN;	/* APB module clock enable */
+	volatile uint32_t CLKODIV;	/* AHB clock output enable and divisor set */
+	volatile uint32_t reserved2;      /* 0x14 */
+	volatile uint32_t RSTCON;	/* reset contrl */
+	volatile uint32_t RSTSTAT;	/* reset status */
+	volatile uint32_t AHBCLKDIV_SEL; /* AHB clock divisor select */
+	volatile uint32_t CLKSEL;	/* main clock source select */
+	volatile uint32_t PLLSTAT;	/* PLL status register */
+	volatile uint32_t PLLCON;	/* PLL control register */
+	volatile uint32_t reserved3;	/* 0x30 */
+	volatile uint32_t AHBCLKEN;	/* AHB module clock enable */
+	volatile uint32_t reserved4[2];  /* 0x38, 0x3c */
+	volatile uint32_t I2S_TX_SCLKDIV; /* I2S TX SCLK divisor */
+	volatile uint32_t I2S_RX_SCLKDIV; /* I2S RX SCLK divisor */
+	volatile uint32_t I2S_RX_SCLKSEL; /* I2S RX SCLK source select */
+	volatile uint32_t SDIO_REFCLK_DIV; /* SDIO reference clock divisor */
+	volatile uint32_t GPIO4B_DBCLK_DIV; /* GPIO4B DBCLK divisor */
+	volatile uint32_t IMAGE_CHK;	/* Image pad status */
+	volatile uint32_t PROT_RANGE;	/* PROT range */
+	volatile uint32_t SPI_MST_CLKDIV; /* SPI master clock divisor */
+	volatile uint32_t DVFS_CLKDIV;	/* DFSS main clock domain divider */
+	volatile uint32_t DVFS_VDDSET;	/* VDD setting */
+	volatile uint32_t DVFS_VWTIME;	/* VDD adjust waiting time */
+	volatile uint32_t PMC_PUWTIME;	/* power up waiting time */
+	volatile uint32_t PMOD_MUX;	/* PMOD IO mux */
+	volatile uint32_t ARDUINO_MUX;	/* arduino IO mux */
+	volatile uint32_t USBPHY_PLL;	/* USBPHY PLL */
+	volatile uint32_t USBCFG;	/* USB configuration */
+	volatile uint32_t TIMER_PAUSE;	/* PWM timer pause */
+	volatile uint32_t GPIO8B_DBCLK_DIV; /* GPIO8B DBCLK divisor */
+	volatile uint32_t RESET_PD_VECTOR; /* reset powerdown vector */
+	volatile uint32_t UART3SCLK_DIV;  /* UART3SCLK_DIV */
+} sysconf_reg_t;
+
+/* CLKSEL_CONST is not described in spec. */
+#define CLKSEL_CONST	(0x5A690000)
+#define CLKSEL_EXT_16M	(0 | CLKSEL_CONST)
+#define CLKSEL_PLL		(1 | CLKSEL_CONST)
+#define CLKSEL_EXT_32K	(2 | CLKSEL_CONST)
+
+#define PLLCON_BIT_OFFSET_N 		0
+#define PLLCON_BIT_OFFSET_M 		4
+#define PLLCON_BIT_OFFSET_OD 		20
+#define PLLCON_BIT_OFFSET_BP 		24
+#define PLLCON_BIT_OFFSET_PLLRST	26
+
+
+#define PLLSTAT_BIT_OFFSET_PLLSTB 	2
+#define PLLSTAT_BIT_OFFSET_PLLRDY 	3
+
+
+#define AHBCLKEN_BIT_I2S		0
+#define AHBCLKEN_BIT_USB		1
+#define AHBCLKEN_BIT_FLASH		2
+#define AHBCLKEN_BIT_FMC		3
+#define AHBCLKEN_BIT_DVFS		4
+#define AHBCLKEN_BIT_PMC		5
+#define AHBCLKEN_BIT_BOOT_SPI		6
+#define AHBCLKEN_BIT_SDIO		7
+
+#define APBCLKEN_BIT_ADC		0
+#define APBCLKEN_BIT_I2S_TX		1
+#define APBCLKEN_BIT_I2S_RX		2
+#define APBCLKEN_BIT_RTC		3
+#define APBCLKEN_BIT_PWM		4
+#define APBCLKEN_BIT_I3C		5
+
+
+#define SPI_MASTER_0			0
+#define SPI_MASTER_1			1
+#define SPI_MASTER_2			2
+
+#define GPIO8B_BANK0			0
+#define GPIO8B_BANK1			1
+#define GPIO8B_BANK2			2
+#define GPIO8B_BANK3			3
+
+#define GPIO4B_BANK0			0
+#define GPIO4B_BANK1			1
+#define GPIO4B_BANK2			2
+
+/* reset caused by power on */
+#define SYS_RST_SOFTWARE_ON		0x2
+
+
+#define DVFS_PERF_LEVEL0		0
+#define DVFS_PERF_LEVEL1		1
+#define DVFS_PERF_LEVEL2		2
+#define DVFS_PERF_LEVEL3		3
+
+/* pmode mux definition */
+#define PMOD_MUX_PMA			(0x1)
+#define PMOD_MUX_PMB			(0x2)
+#define PMOD_MUX_PMC			(0x4)
+
+/* arduino mux definition */
+#define ARDUINO_MUX_UART		(0x1)
+#define ARDUINO_MUX_SPI			(0x2)
+#define ARDUINO_MUX_PWM0		(0x4)
+#define ARDUINO_MUX_PWM1		(0x8)
+#define ARDUINO_MUX_PWM2		(0x10)
+#define ARDUINO_MUX_PWM3		(0x20)
+#define ARDUINO_MUX_PWM4		(0x40)
+#define ARDUINO_MUX_PWM5		(0x80)
+#define ARDUINO_MUX_I2C			(0x100)
+#define ARDUINO_MUX_ADC0		(0x400)
+#define ARDUINO_MUX_ADC1		(0x800)
+#define ARDUINO_MUX_ADC2		(0x1000)
+#define ARDUINO_MUX_ADC3		(0x2000)
+#define ARDUINO_MUX_ADC4		(0x4000)
+#define ARDUINO_MUX_ADC5		(0x8000)
+
+#define PWM_TIMER0			0
+#define PWM_TIMER1			1
+#define PWM_TIMER2			2
+#define PWM_TIMER3			3
+#define PWM_TIMER4			4
+#define PWM_TIMER5			5
+
+
+extern void arc_iot_pll_conf_reg(uint32_t val);
+extern int32_t arc_iot_pll_fout_config(uint32_t freq);
+extern void arc_iot_ahb_clk_divisor(uint8_t div);
+extern void arc_iot_ahb_clk_enable(uint8_t dev);
+extern void arc_iot_ahb_clk_disable(uint8_t dev);
+extern void arc_iot_sdio_clk_divisor(uint8_t div);
+extern void arc_iot_spi_master_clk_divisor(uint8_t id, uint8_t div);
+extern void arc_iot_gpio8b_dbclk_div(uint8_t bank, uint8_t div);
+extern void arc_iot_gpio4b_dbclk_div(uint8_t bank, uint8_t div);
+extern void arc_iot_i2s_tx_clk_div(uint8_t div);
+extern void arc_iot_i2s_rx_clk_div(uint8_t div);
+extern void arc_iot_i2s_rx_clk_sel(uint8_t sel);
+extern void arc_iot_syscon_reset(void);
+extern uint32_t arc_iot_is_poweron_rst(void);
+extern void arc_iot_dvfs_clk_divisor(uint8_t level, uint8_t div);
+extern void arc_iot_dvfs_vdd_config(uint8_t level, uint8_t val);
+extern void arc_iot_dvfs_vwtime_config(uint8_t time);
+extern void arc_iot_pmc_pwwtime_config(uint8_t time);
+extern void arc_iot_uart3_clk_divisor(uint8_t div);
+extern void arc_iot_reset_powerdown_vector(uint32_t addr);
+extern void arc_iot_eflash_clk_div(uint8_t div);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ARC_IOT_SYSCONF_H_ */

soc/snps/emsdp/CMakeLists.txt

@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: Apache-2.0
+zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata)
+
+if(CONFIG_SOC_EMSDP_EM4)
+  zephyr_compile_options(-mmpy-option=3  -mno-div-rem)
+elseif(CONFIG_SOC_EMSDP_EM6)
+  zephyr_compile_options(-mmpy-option=3  -mno-div-rem)
+elseif(CONFIG_SOC_EMSDP_EM5D)
+  zephyr_compile_options(-mmpy-option=6)
+elseif(CONFIG_SOC_EMSDP_EM7D)
+  zephyr_compile_options(-mmpy-option=6)
+elseif(CONFIG_SOC_EMSDP_EM7D_ESP)
+  zephyr_compile_options(-mmpy-option=6)
+elseif(CONFIG_SOC_EMSDP_EM9D)
+  zephyr_compile_options(-mmpy-option=6)
+  zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpus_all)
+elseif(CONFIG_SOC_EMSDP_EM11D)
+  zephyr_compile_options(-mmpy-option=6)
+  zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all)
+endif()
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/snps/emsdp/Kconfig

@@ -0,0 +1,32 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ARC_EMSDP
+	select ARC
+
+config SOC_EMSDP_EM4
+	select CPU_HAS_MPU
+
+config SOC_EMSDP_EM5D
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU
+
+config SOC_EMSDP_EM6
+	select CPU_HAS_MPU
+
+config SOC_EMSDP_EM7D
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU
+
+config SOC_EMSDP_EM7D_ESP
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU
+	select ARC_HAS_SECURE
+
+config SOC_EMSDP_EM9D
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU
+
+config SOC_EMSDP_EM11D
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU

soc/snps/emsdp/Kconfig.defconfig

@@ -0,0 +1,13 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_ARC_EMSDP
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+rsource "Kconfig.defconfig.*"
+
+endif # SOC_ARC_EMSDP

soc/snps/emsdp/Kconfig.defconfig.em11d

@@ -0,0 +1,43 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EMSDP_EM11D
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 40000000
+
+config CPU_EM4_FPUDA
+	default y
+
+config ARC_MPU_VER
+	default 2
+
+config RGF_NUM_BANKS
+	default 2
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+config FP_FPU_DA
+	default y
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+config ZTEST_STACK_SIZE
+	default 2048
+	depends on ZTEST
+
+config NUM_IRQS
+	default 111
+
+endif # SOC_EMSDP_EM11D

soc/snps/emsdp/Kconfig.defconfig.em4

@@ -0,0 +1,43 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EMSDP_EM4
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 50000000
+
+config CPU_EM4
+	default y
+
+config ARC_MPU_VER
+	default 2
+
+config RGF_NUM_BANKS
+	default 2
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+config CACHE_MANAGEMENT
+	default n
+
+config FP_FPU_DA
+	default n
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+config ZTEST_STACK_SIZE
+	default 2048
+	depends on ZTEST
+
+config NUM_IRQS
+	default 113
+
+endif # SOC_EMSDP_EM4

soc/snps/emsdp/Kconfig.defconfig.em5d

@@ -0,0 +1,43 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EMSDP_EM5D
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 40000000
+
+config CPU_EM4_FPUDA
+	default y
+
+config ARC_MPU_VER
+	default 2
+
+config RGF_NUM_BANKS
+	default 2
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+config CACHE_MANAGEMENT
+	default n
+
+config FP_FPU_DA
+	default y
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+config ZTEST_STACK_SIZE
+	default 2048
+	depends on ZTEST
+
+config NUM_IRQS
+	default 111
+
+endif # SOC_EMSDP_EM5D

soc/snps/emsdp/Kconfig.defconfig.em6

@@ -0,0 +1,43 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EMSDP_EM6
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 50000000
+
+config CPU_EM6
+	default y
+
+config ARC_MPU_VER
+	default 2
+
+config RGF_NUM_BANKS
+	default 2
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+config FP_FPU_DA
+	default n
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+config ZTEST_STACK_SIZE
+	default 2048
+	depends on ZTEST
+
+config NUM_IRQS
+	default 113
+
+endif # SOC_EMSDP_EM6

soc/snps/emsdp/Kconfig.defconfig.em7d

@@ -0,0 +1,43 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EMSDP_EM7D
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 40000000
+
+config CPU_EM4_FPUDA
+	default y
+
+config ARC_MPU_VER
+	default 2
+
+config RGF_NUM_BANKS
+	default 2
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+config FP_FPU_DA
+	default y
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+config ZTEST_STACK_SIZE
+	default 2048
+	depends on ZTEST
+
+config NUM_IRQS
+	default 111
+
+endif # SOC_EMSDP_EM7D

soc/snps/emsdp/Kconfig.defconfig.em7d_esp

@@ -0,0 +1,33 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EMSDP_EM7D_ESP
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 50000000
+
+config CPU_EM4_FPUDA
+	default y
+
+config ARC_MPU_VER
+	default 4
+
+config RGF_NUM_BANKS
+	default 1
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default n
+
+config CACHE_MANAGEMENT
+	default y
+
+config FP_FPU_DA
+	default y
+
+config NUM_IRQS
+	default 112
+
+endif # SOC_EMSDP_EM7D_ESP

soc/snps/emsdp/Kconfig.defconfig.em9d

@@ -0,0 +1,43 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EMSDP_EM9D
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 40000000
+
+config CPU_EM4_FPUDA
+	default y
+
+config ARC_MPU_VER
+	default 2
+
+config RGF_NUM_BANKS
+	default 2
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+config CACHE_MANAGEMENT
+	default n
+
+config FP_FPU_DA
+	default y
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+config ZTEST_STACK_SIZE
+	default 2048
+	depends on ZTEST
+
+config NUM_IRQS
+	default 111
+
+endif # SOC_EMSDP_EM9D

soc/snps/emsdp/Kconfig.soc

@@ -0,0 +1,59 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ARC_EMSDP
+	bool
+
+config SOC_EMSDP_EM4
+	bool
+	select SOC_ARC_EMSDP
+	help
+	  Synopsys ARC EM4 of EMSDP
+
+config SOC_EMSDP_EM5D
+	bool
+	select SOC_ARC_EMSDP
+	help
+	  Synopsys ARC EM5D of EMSDP
+
+config SOC_EMSDP_EM6
+	bool
+	select SOC_ARC_EMSDP
+	help
+	  Synopsys ARC EM6 of EMSDP
+
+config SOC_EMSDP_EM7D
+	bool
+	select SOC_ARC_EMSDP
+	help
+	  Synopsys ARC EM7D of EMSDP
+
+config SOC_EMSDP_EM7D_ESP
+	bool
+	select SOC_ARC_EMSDP
+	help
+	  Synopsys ARC EM7D+ESP of EMSDP
+
+config SOC_EMSDP_EM9D
+	bool
+	select SOC_ARC_EMSDP
+	help
+	  Synopsys ARC EM9D of EMSDP
+
+config SOC_EMSDP_EM11D
+	bool
+	select SOC_ARC_EMSDP
+	help
+	  Synopsys ARC EM11D of EMSDP
+
+config SOC_SERIES
+	default "emsdp" if SOC_ARC_EMSDP
+
+config SOC
+	default "emsdp_em4" if SOC_EMSDP_EM4
+	default "emsdp_em5d" if SOC_EMSDP_EM5D
+	default "emsdp_em6" if SOC_EMSDP_EM6
+	default "emsdp_em7d" if SOC_EMSDP_EM7D
+	default "emsdp_em7d_esp" if SOC_EMSDP_EM7D_ESP
+	default "emsdp_em9d" if SOC_EMSDP_EM9D
+	default "emsdp_em11d" if SOC_EMSDP_EM11D

soc/snps/emsdp/linker.ld

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the Synopsys ARC IoT Development Kit
+ */
+
+#include <zephyr/devicetree.h>
+
+/*
+ * SRAM base address and size
+ *
+ */
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
+    (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
+#define SRAM_START		DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
+#define SRAM_SIZE		DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
+#endif
+
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#if DT_NODE_HAS_PROP(DT_INST(0, arc_iccm), reg) && \
+    (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
+#define ICCM_START		DT_REG_ADDR(DT_INST(0, arc_iccm))
+#define ICCM_SIZE		DT_REG_SIZE(DT_INST(0, arc_iccm))
+#endif
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#if DT_NODE_HAS_PROP(DT_INST(0, arc_dccm), reg) && \
+    (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
+#define DCCM_START		DT_REG_ADDR(DT_INST(0, arc_dccm))
+#define DCCM_SIZE		DT_REG_SIZE(DT_INST(0, arc_dccm))
+#endif
+
+#include <zephyr/arch/arc/v2/xy_mem.ld>
+#include <zephyr/arch/arc/v2/linker.ld>

soc/snps/emsdp/pinctrl_soc.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2023 Synopsys
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_ARC_SNPS_EMSDP_PINCTRL_H_
+#define ZEPHYR_SOC_ARC_SNPS_EMSDP_PINCTRL_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+
+typedef struct pinctrl_soc_pin_t {
+	uint8_t pin;
+	uint8_t type;
+} pinctrl_soc_pin_t;
+
+#define EMSDP_DT_PIN(node_id)					\
+	{							\
+		.pin = DT_PROP_BY_IDX(node_id, pinmux, 0),	\
+		.type = DT_PROP_BY_IDX(node_id, pinmux, 1)	\
+	},
+
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)		\
+	EMSDP_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx))
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)		\
+	{ DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) }
+
+#endif /* ZEPHYR_SOC_ARC_SNPS_EMSDP_PINCTRL_H_ */

soc/snps/emsdp/soc.yml

@@ -0,0 +1,10 @@
+series:
+- name: emsdp
+  socs:
+  - name: emsdp_em4
+  - name: emsdp_em5d
+  - name: emsdp_em6
+  - name: emsdp_em7d
+  - name: emsdp_em7d_esp
+  - name: emsdp_em9d
+  - name: emsdp_em11d

soc/snps/emsk/CMakeLists.txt

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata -mmpy-option=6)
+
+if(CONFIG_SOC_EMSK_EM9D)
+  zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpus_all)
+elseif(CONFIG_SOC_EMSK_EM11D)
+  zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all)
+endif()
+
+zephyr_sources(soc_config.c)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/snps/emsk/Kconfig

@@ -0,0 +1,15 @@
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_EMSK
+	select ARC
+
+config SOC_EMSK_EM7D
+	select CPU_HAS_MPU
+
+config SOC_EMSK_EM9D
+	select CPU_HAS_FPU
+
+config SOC_EMSK_EM11D
+	select CPU_HAS_FPU

soc/snps/emsk/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EMSK
+
+rsource "Kconfig.defconfig.*"
+
+endif # SOC_EMSK

soc/snps/emsk/Kconfig.defconfig.em11d

@@ -0,0 +1,35 @@
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EMSK_EM11D
+
+config CPU_EM4_FPUDA
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 38 if "$(BOARD_REVISION)" = "2.3"
+	default 36 if "$(BOARD_REVISION)" = "2.2"
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	default n
+
+config CACHE_MANAGEMENT
+	default y
+
+config FP_FPU_DA
+	default y
+
+endif # SOC_EMSK_EM11D

soc/snps/emsk/Kconfig.defconfig.em7d

@@ -0,0 +1,55 @@
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EMSK_EM7D
+
+config CPU_EM4_DMIPS
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 38 if "$(BOARD_REVISION)" = "2.3"
+	default 36 if "$(BOARD_REVISION)" = "2.2"
+
+config ARC_MPU_VER
+	default 4 if "$(BOARD_REVISION)" = "2.3"
+	default 2 if "$(BOARD_REVISION)" = "2.2"
+
+config RGF_NUM_BANKS
+	default 1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 25000000 if "$(BOARD_REVISION)" = "2.3"
+	default 30000000 if "$(BOARD_REVISION)" = "2.2"
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default n if "$(BOARD_REVISION)" = "2.3"
+	default y if "$(BOARD_REVISION)" = "2.2"
+
+config CACHE_MANAGEMENT
+	default y
+
+if (ARC_MPU_VER = 2)
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+config ZTEST_STACK_SIZE
+	default 2048
+	depends on ZTEST
+
+endif # ARC_MPU_VER
+
+endif # SOC_EMSK_EM7D

soc/snps/emsk/Kconfig.defconfig.em9d

@@ -0,0 +1,29 @@
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_EMSK_EM9D
+
+config CPU_EM4_FPUS
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 38 if "$(BOARD_REVISION)" = "2.3"
+	default 36 if "$(BOARD_REVISION)" = "2.2"
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 20000000
+
+config HARVARD
+	default y
+
+endif # SOC_EMSK_EM9D

soc/snps/emsk/Kconfig.soc

@@ -0,0 +1,34 @@
+# Copyright (c) 2014 Wind River Systems, Inc.
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_EMSK
+	bool
+	help
+	  Synopsys ARC EM Starter Kit SoC
+
+config SOC_EMSK_EM7D
+	bool
+	select SOC_EMSK
+	help
+	  Synopsys ARC EM7D of EMSK
+
+config SOC_EMSK_EM9D
+	bool
+	select SOC_EMSK
+	help
+	  Synopsys ARC EM9D of EMSK
+
+config SOC_EMSK_EM11D
+	bool
+	select SOC_EMSK
+	help
+	  Synopsys ARC EM11D of EMSK
+
+config SOC_SERIES
+	default "emsk" if SOC_EMSK
+
+config SOC
+	default "emsk_em7d" if SOC_EMSK_EM7D
+	default "emsk_em9d" if SOC_EMSK_EM9D
+	default "emsk_em11d" if SOC_EMSK_EM11D

soc/snps/emsk/linker.ld

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit platform.
+ */
+
+#include <zephyr/devicetree.h>
+
+/*
+ * DRAM base address and size
+ *
+ * DRAM includes the exception vector table at reset, which is at
+ * the beginning of the region.
+ */
+#if DT_NODE_HAS_PROP(DT_NODELABEL(ddr0), reg) && \
+    (DT_REG_SIZE(DT_NODELABEL(ddr0)) > 0)
+#define SRAM_START		DT_REG_ADDR(DT_NODELABEL(ddr0))
+#define SRAM_SIZE		DT_REG_SIZE(DT_NODELABEL(ddr0))
+#endif
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#if DT_NODE_HAS_PROP(DT_INST(0, arc_iccm), reg) && \
+    (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
+#define ICCM_START		DT_REG_ADDR(DT_INST(0, arc_iccm))
+#define ICCM_SIZE		DT_REG_SIZE(DT_INST(0, arc_iccm))
+#endif
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#if DT_NODE_HAS_PROP(DT_INST(0, arc_dccm), reg) && \
+    (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
+#define DCCM_START		DT_REG_ADDR(DT_INST(0, arc_dccm))
+#define DCCM_SIZE		DT_REG_SIZE(DT_INST(0, arc_dccm))
+#endif
+
+#include <zephyr/arch/arc/v2/xy_mem.ld>
+#include <zephyr/arch/arc/v2/linker.ld>

soc/snps/emsk/soc.yml

@@ -0,0 +1,6 @@
+series:
+- name: emsk
+  socs:
+  - name: emsk_em7d
+  - name: emsk_em9d
+  - name: emsk_em11d

soc/snps/emsk/soc_config.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/init.h>
+
+
+#ifdef CONFIG_UART_NS16550
+
+static int uart_ns16550_init(void)
+{
+
+	/* On ARC EM Starter kit board,
+	 * send the UART the command to clear the interrupt
+	 */
+#if DT_NODE_HAS_STATUS(DT_INST(0, ns16550), okay)
+	sys_write32(0, DT_REG_ADDR(DT_INST(0, ns16550))+0x4);
+	sys_write32(0, DT_REG_ADDR(DT_INST(0, ns16550))+0x10);
+#endif /* DT_NODE_HAS_STATUS(DT_INST(0, ns16550), okay) */
+#if DT_NODE_HAS_STATUS(DT_INST(1, ns16550), okay)
+	sys_write32(0, DT_REG_ADDR(DT_INST(1, ns16550))+0x4);
+	sys_write32(0, DT_REG_ADDR(DT_INST(1, ns16550))+0x10);
+#endif /* DT_NODE_HAS_STATUS(DT_INST(1, ns16550), okay) */
+
+	return 0;
+}
+
+SYS_INIT(uart_ns16550_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif /* CONFIG_UART_NS16550 */

soc/snps/hsdk/CMakeLists.txt

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+
+if(COMPILER STREQUAL gcc)
+  # GNU compiler options
+  # -mcpu=hs38_linux includes -matomic -mcode-density -mdiv-rem
+  # -mswap -mnorm -mll64 -mmpy-option=9 -mfpu=fpud_all
+  zephyr_cc_option(-mcpu=${GCC_M_CPU})
+  zephyr_cc_option(-mno-sdata)
+  zephyr_cc_option_ifdef(CONFIG_FPU -mfpu=fpud_all)
+else()
+  # MWDT compiler options
+  zephyr_compile_options(-arcv2hs -core2 -Xatomic -Xll64 -Xunaligned -Xcode_density
+		   -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh
+		   -Xshift_assist -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc)
+  zephyr_compile_options_ifdef(CONFIG_FPU -Xfpu_mac -Xfpud_div)
+
+  zephyr_ld_options(-Hlib=hs38_full)
+endif()
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/snps/hsdk/Kconfig

@@ -0,0 +1,6 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ARC_HSDK
+	select ARC
+	select CPU_HAS_FPU

soc/snps/hsdk/Kconfig.defconfig

@@ -0,0 +1,46 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_ARC_HSDK
+
+config CPU_HS3X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 2 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 88
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 500000000
+
+config ARC_FIRQ
+	default y
+
+config CODE_DENSITY
+	default y
+
+config ARCV2_TIMER_IRQ_PRIORITY
+	default 1
+
+config ARC_CONNECT
+	default y
+
+config MP_MAX_NUM_CPUS
+	default 4
+
+config UART_NS16550_ACCESS_WORD_ONLY
+	default y
+	depends on UART_NS16550
+
+config ARC_HAS_ACCL_REGS
+	default y
+
+endif # ARC_HSDK

soc/snps/hsdk/Kconfig.soc

@@ -0,0 +1,8 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ARC_HSDK
+	bool
+
+config SOC
+	default "arc_hsdk" if SOC_ARC_HSDK

soc/snps/hsdk/linker.ld

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the HS Development Kit
+ */
+
+#include <zephyr/devicetree.h>
+
+/*
+ * SRAM base address and size
+ */
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
+    (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
+#define SRAM_START		DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
+#define SRAM_SIZE		DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
+#endif
+
+#include <zephyr/arch/arc/v2/linker.ld>

soc/snps/hsdk/soc.yml

@@ -0,0 +1,4 @@
+series:
+- name: arc_hsdk
+  socs:
+  - name: arc_hsdk

soc/snps/hsdk4xd/CMakeLists.txt

@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(COMPILER STREQUAL gcc)
+  # GNU compiler options
+  zephyr_compile_options(-mno-sdata)
+  zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpud_all)
+else()
+  # MWDT compiler options
+   zephyr_compile_options(-arcv2hs -core4 -Xdual_issue -Xcode_density -Hrgf_banked_regs=32 -HL
+    -Xatomic -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
+    -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc -Hld_cycles=2)
+
+  zephyr_compile_options_ifdef(CONFIG_FPU -Xfpu_mac -Xfpud_div)
+
+  zephyr_ld_options(-Hlib=hs48_slc_full)
+endif()
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/snps/hsdk4xd/Kconfig

@@ -0,0 +1,7 @@
+# Copyright (c) 2023 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ARC_HSDK4XD
+	select ARC
+	select CPU_HAS_FPU
+	select CPU_HAS_DSP

soc/snps/hsdk4xd/Kconfig.defconfig

@@ -0,0 +1,53 @@
+# Copyright (c) 2023 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_ARC_HSDK4XD
+
+config CPU_HS4X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 2 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 88
+
+config RGF_NUM_BANKS
+	# Actually cpu has 4 banks but zephys currently supports up to 2
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 500000000
+
+config ARC_FIRQ
+	default y
+
+config CODE_DENSITY
+	default y
+
+config ARCV2_TIMER_IRQ_PRIORITY
+	default 1
+
+config ARC_CONNECT
+	default y
+
+config MP_MAX_NUM_CPUS
+	default 4
+
+config UART_NS16550_ACCESS_WORD_ONLY
+	default y
+	depends on UART_NS16550
+
+config ARC_HAS_ACCL_REGS
+	default y
+
+config ARC_EARLY_SOC_INIT
+	default y
+
+config ARC_HAS_STACK_CHECKING
+	default n
+
+endif # SOC_ARC_HS4XD

soc/snps/hsdk4xd/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2023 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ARC_HSDK4XD
+	bool
+	help
+	  Synopsys ARC HSDK4XD SoC
+
+config SOC
+	default "arc_hsdk4xd" if SOC_ARC_HSDK4XD

soc/snps/hsdk4xd/linker.ld

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2023 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the HSDK4XD Development Kit
+ */
+
+#include <zephyr/devicetree.h>
+
+/*
+ * SRAM base address and size
+ */
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
+#define SRAM_START		DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
+#define SRAM_SIZE		DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
+#endif
+
+#include <zephyr/arch/arc/v2/linker.ld>

soc/snps/hsdk4xd/soc.yml

@@ -0,0 +1,4 @@
+series:
+- name: arc_hsdk4xd
+  socs:
+  - name: arc_hsdk4xd

soc/snps/hsdk4xd/soc_ctrl.h

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2023 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ARC_HSDK4XD_SOC_CTRL_H_
+#define _ARC_HSDK4XD_SOC_CTRL_H_
+
+#ifdef _ASMLANGUAGE
+.macro soc_early_asm_init_percpu
+	mov  r0, 1	/* disable LPB for HS4XD */
+	sr   r0, [_ARC_V2_LPB_CTRL]
+.endm
+#endif /* _ASMLANGUAGE */
+
+#endif /* _ARC_HSDK4XD_SOC_CTRL_H_ */

soc/snps/hsdk4xd/tune_build_ops.cmake

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(GCC_ARC_TUNED_CPU hs4xd)

soc/snps/nsim/CMakeLists.txt

@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(COMPILER STREQUAL gcc)
+  # GNU compiler options
+  zephyr_compile_options(-mcpu=${GCC_M_CPU})
+  if(CONFIG_ISA_ARCV2)
+    # ISA_ARCV2 & 32BIT
+    zephyr_compile_options(-mno-sdata)
+    zephyr_compile_options_ifdef(CONFIG_CPU_ARCEM -mmpy-option=wlh1)
+    zephyr_compile_options_ifdef(CONFIG_CPU_ARCHS -mmpy-option=plus_qmacw)
+    if(CONFIG_CPU_ARCHS)
+      zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpud_all)
+    else()
+      zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all)
+    endif()
+  endif()
+
+  if(CONFIG_SOC_NSIM_VPX5)
+    message(FATAL_ERROR "ARC VPX targets can be built with ARC MWDT toolchain only")
+  endif()
+else()
+  # MWDT compiler options
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM -arcv2em -core3 -Xdiv_rem=radix2
+			       -Xmpy_option=mpyd -Xbitscan -Xswap -Xbarrel_shifter
+			       -Xshift_assist -Xdsp2 -Xdsp_complex
+			       -Xdsp_divsqrt=radix2 -Xdsp_itu -Xdsp_accshift=full
+			       -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
+			       -Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM11D -arcv2em -core3 -Xdiv_rem=radix2
+			       -Xbitscan -Xswap -Xbarrel_shifter
+			       -Xshift_assist -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
+			       -Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_EM11D -Hlib=em9d_nrg_fpusp -Hdsplib)
+
+  if(CONFIG_SOC_NSIM_EM11D)
+    set_property(GLOBAL PROPERTY z_arc_dsp_options -Xxy -Xagu_large -Hfxapi -Xdsp2
+              -Xdsp_accshift=full -Xdsp_divsqrt=radix2 -Xdsp_complex -Xdsp_itu
+              -Xdsp_ctrl=postshift,noguard,convergent -Xmpy_option=mpyd)
+  endif()
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_SEM -arcv2em -core3 -Xcode_density
+			       -Xdiv_rem=radix2 -Xswap -Xbitscan -Xmpy_option=mpyd
+			       -Xshift_assist -Xbarrel_shifter -Xdsp2
+			       -Xdsp_complex -Xdsp_divsqrt=radix2
+			       -Xdsp_accshift=limited -Xtimer0 -Xtimer1
+			       -Xsec_timer0 -Xstack_check -Xsec_modes -Xdmac)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS -arcv2hs -core2 -Xatomic
+			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
+			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
+			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
+			       -Xtimer0 -Xtimer1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS -Hlib=hs38_full)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS_SMP -arcv2hs -core2 -Xatomic
+			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
+			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
+			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
+			       -Xtimer0 -Xtimer1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_SMP -Hlib=hs38_full)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -arcv2hs -core2 -Xatomic
+			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
+			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
+			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
+			       -Xtimer0 -Xtimer1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -Hlib=hs38_full)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_VPX5 -arcv2hs -core4 -uarch_rev=1:4 -Xcode_density
+             -HL -Xatomic -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh
+             -Xshift_assist -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a
+             -Hld_cycles=1 -DDCCM_SYSTEM_BASE_CORE0=0x80000000 -Hccm
+             -DICCM0_SYSTEM_BASE_CORE0=0x0000000 -Xstu=4 -Xvdsp4 -Xvec_unit_rev_minor=1
+             -Xvec_width=512 -Xvec_mem_size=256k -Xvec_mem_bank_width=16 -Xvec_max_fetch_size=16
+             -Xvec_num_slots=3 -Xvec_super_with_scalar -Xvec_regs=40 -Xvec_num_rd_ports=6
+             -Xvec_num_acc=8 -Xvec_num_mpy=2 -Xvec_mpy32 -Xvec_num_alu=3 -Xvec_guard_bit_option=2
+             -Xvec_stack_check -DVEC_MEM_SYS_BASE_CORE0=0xb4000000)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_VPX5 -Hlib=vpx5_integer_full)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS5X -arcv3hs -core0 -Xdual_issue -uarch_rev=0:0
+			       -HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
+			       -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS5X -Hlib=hs58_full)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS5X_SMP -arcv3hs -core0 -Xdual_issue -uarch_rev=0:0
+             -HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
+             -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS5X_SMP -Hlib=hs58_full)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS6X -arc64 -core0 -uarch_rev=0:0 -HL -Xatomic=2
+             -Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS6X -Hlib=hs68_full_zephyr)
+
+  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS6X_SMP -arc64 -core0 -uarch_rev=0:0 -HL -Xatomic=2
+             -Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS6X_SMP -Hlib=hs68_full_zephyr)
+endif()
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/snps/nsim/Kconfig

@@ -0,0 +1,32 @@
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_NSIM
+	select ARC
+
+config SOC_NSIM_EM
+	select CPU_HAS_MPU
+
+config SOC_NSIM_EM7D_V22
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU
+
+config SOC_NSIM_EM11D
+	select CPU_HAS_MPU
+	select CPU_HAS_DSP
+
+config SOC_NSIM_SEM
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU
+	select ARC_HAS_SECURE
+
+config SOC_NSIM_HS
+	select CPU_HAS_FPU
+	select CPU_HAS_MPU
+
+config SOC_NSIM_HS_SMP
+	select CPU_HAS_FPU
+
+config SOC_NSIM_HS_MPUV6
+	select CPU_HAS_MPU
+	select CPU_HAS_FPU

soc/snps/nsim/Kconfig.defconfig

@@ -0,0 +1,11 @@
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM
+
+config XIP
+	default n
+
+rsource "Kconfig.defconfig.*"
+
+endif # SOC_NSIM

soc/snps/nsim/Kconfig.defconfig.em

@@ -0,0 +1,56 @@
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_EM
+
+config CPU_EM4_FPUDA
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config ARC_MPU_VER
+	default 2
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 5000000
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+config FP_FPU_DA
+	default y
+
+if (ARC_MPU_VER = 2)
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+config ZTEST_STACK_SIZE
+	default 2048
+	depends on ZTEST
+
+endif # ARC_MPU_VER
+
+config ARC_HAS_ACCL_REGS
+	default y
+
+endif # SOC_NSIM_EM

soc/snps/nsim/Kconfig.defconfig.em11d

@@ -0,0 +1,62 @@
+# Copyright (c) 2022 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_EM11D
+
+config CPU_EM6
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config ARC_MPU_VER
+	default 2
+
+config RGF_NUM_BANKS
+	default 1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 5000000
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default n
+
+config CACHE_MANAGEMENT
+	default y
+
+config FP_FPU_DA
+	default y
+
+if (ARC_MPU_VER = 2)
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+config ZTEST_STACK_SIZE
+	default 2048
+	depends on ZTEST
+
+endif # ARC_MPU_VER
+
+config ARC_HAS_ACCL_REGS
+	default y
+
+config ARC_XY_ENABLE
+	default y
+
+config ARC_AGU_LARGE
+	default y
+
+endif # SOC_NSIM_EM11D

soc/snps/nsim/Kconfig.defconfig.em7d_v22

@@ -0,0 +1,53 @@
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_EM7D_V22
+
+config CPU_EM4_FPUDA
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config ARC_MPU_VER
+	default 2
+
+config RGF_NUM_BANKS
+	default 1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 5000000
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+if (ARC_MPU_VER = 2)
+
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 2048
+
+config ZTEST_STACK_SIZE
+	default 2048
+	depends on ZTEST
+
+endif # ARC_MPU_VER
+
+config ARC_HAS_ACCL_REGS
+	default y
+
+endif # SOC_NSIM_EM

soc/snps/nsim/Kconfig.defconfig.hs

@@ -0,0 +1,36 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_HS
+
+config CPU_HS3X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 16 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 5000000
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+config ARC_MPU_VER
+	default 3
+
+endif # SOC_NSIM_HS

soc/snps/nsim/Kconfig.defconfig.hs5x

@@ -0,0 +1,23 @@
+# Copyright (c) 2022 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_HS5X
+
+config CPU_HS5X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 16 priority levels:
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 5000000
+
+config CACHE_MANAGEMENT
+	default y
+
+endif # SOC_NSIM_HS5X

soc/snps/nsim/Kconfig.defconfig.hs5x_smp

@@ -0,0 +1,29 @@
+# Copyright (c) 2022 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_HS5X_SMP
+
+config CPU_HS5X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 16 priority levels:
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 5000000
+
+config CACHE_MANAGEMENT
+	default y
+
+config ARC_CONNECT
+	default y
+
+config MP_MAX_NUM_CPUS
+	default 2
+
+endif # SOC_NSIM_HS5X_SMP

soc/snps/nsim/Kconfig.defconfig.hs6x

@@ -0,0 +1,23 @@
+# Copyright (c) 2021 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_HS6X
+
+config CPU_HS6X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 16 priority levels:
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 50000000
+
+config CACHE_MANAGEMENT
+	default y
+
+endif # SOC_NSIM_HS6X

soc/snps/nsim/Kconfig.defconfig.hs6x_smp

@@ -0,0 +1,30 @@
+# Copyright (c) 2021 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_HS6X_SMP
+
+config CPU_HS6X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 16 priority levels:
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	# SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
+	default 1000000
+
+config CACHE_MANAGEMENT
+	default y
+
+config ARC_CONNECT
+	default y
+
+config MP_MAX_NUM_CPUS
+	default 2
+
+endif # SOC_NSIM_HS6X_SMP

soc/snps/nsim/Kconfig.defconfig.hs_mpuv6

@@ -0,0 +1,39 @@
+# Copyright (c) 2021 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_HS_MPUV6
+
+config CPU_HS3X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 16 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config ARC_MPU_VER
+	default 6
+
+config MAX_DOMAIN_PARTITIONS
+	default 32 if USERSPACE
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 5000000
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+endif # SOC_NSIM_HS_MPUV6

soc/snps/nsim/Kconfig.defconfig.hs_smp

@@ -0,0 +1,37 @@
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_HS_SMP
+
+config CPU_HS3X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 16 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 88
+
+config RGF_NUM_BANKS
+	default 2
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+        # SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
+	default 1000000
+
+config ARC_FIRQ
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+config ARC_CONNECT
+	default y
+
+config MP_MAX_NUM_CPUS
+	default 2
+
+endif # SOC_NSIM_HS_SMP

soc/snps/nsim/Kconfig.defconfig.sem

@@ -0,0 +1,39 @@
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_SEM
+
+config CPU_EM4_FPUDA
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 4 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config ARC_MPU_VER
+	default 4
+
+config RGF_NUM_BANKS
+	default 1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 5000000
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default n
+
+config CACHE_MANAGEMENT
+	default y
+
+config ARC_HAS_ACCL_REGS
+	default y
+
+endif # SOC_NSIM_SEM

soc/snps/nsim/Kconfig.defconfig.vpx5

@@ -0,0 +1,33 @@
+# Copyright (c) 2023 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_VPX5
+
+config CPU_HS3X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 16 priority levels:
+	# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
+	default 4
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 24
+
+config RGF_NUM_BANKS
+	default 1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 5000000
+
+config HARVARD
+	default y
+
+config ARC_FIRQ
+	default n
+
+config CACHE_MANAGEMENT
+	default y
+
+endif # SOC_NSIM_VPX5

soc/snps/nsim/Kconfig.soc

@@ -0,0 +1,94 @@
+# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_NSIM
+	bool
+
+config SOC_NSIM_EM
+	bool
+	select SOC_NSIM
+	help
+	  Synopsys ARC EM4 in nSIM
+
+config SOC_NSIM_EM7D_V22
+	bool
+	select SOC_NSIM
+	help
+	  Synopsys ARC EM7D_V22 in nSIM
+
+config SOC_NSIM_EM11D
+	bool
+	select SOC_NSIM
+	help
+	  Synopsys ARC EM11D in nSIM
+
+config SOC_NSIM_SEM
+	bool
+	select SOC_NSIM
+	help
+	  Synopsys ARC SEM in nSIM
+
+config SOC_NSIM_HS
+	bool
+	select SOC_NSIM
+	help
+	  Synopsys ARC HS3X in nSIM
+
+config SOC_NSIM_HS_SMP
+	bool
+	select SOC_NSIM
+	help
+	  Multi-core Synopsys ARC HS3X in nSIM
+
+config SOC_NSIM_HS_MPUV6
+	bool
+	select SOC_NSIM
+	help
+	  Synopsys ARC HS3X with MPU v6 in nSIM
+
+config SOC_NSIM_VPX5
+	bool
+	select SOC_NSIM
+	help
+	  Synopsys ARC VPX5 in nSIM
+
+config SOC_NSIM_HS5X
+	bool
+	select SOC_NSIM
+	help
+	  Synopsys ARC HS5x in nSIM
+
+config SOC_NSIM_HS5X_SMP
+	bool
+	select SOC_NSIM
+	help
+	  Multi-core Synopsys ARC HS5x in nSIM
+
+config SOC_NSIM_HS6X
+	bool
+	select SOC_NSIM
+	help
+	  Synopsys ARC HS6x in nSIM
+
+config SOC_NSIM_HS6X_SMP
+	bool
+	select SOC_NSIM
+	help
+	  Multi-core Synopsys ARC HS6x in nSIM
+
+config SOC
+	default "nsim_em" if SOC_NSIM_EM
+	default "nsim_em7d_v22" if SOC_NSIM_EM7D_V22
+	default "nsim_em11d" if SOC_NSIM_EM11D
+	default "nsim_sem" if SOC_NSIM_SEM
+	default "nsim_hs" if SOC_NSIM_HS
+	default "nsim_hs_smp" if SOC_NSIM_HS_SMP
+	default "nsim_hs_mpuv6" if SOC_NSIM_HS_MPUV6
+	default "nsim_vpx5" if SOC_NSIM_VPX5
+	default "nsim_hs5x" if SOC_NSIM_HS5X
+	default "nsim_hs5x_smp" if SOC_NSIM_HS5X_SMP
+	default "nsim_hs6x" if SOC_NSIM_HS6X
+	default "nsim_hs6x_smp" if SOC_NSIM_HS6X_SMP
+
+config SOC_SERIES
+	default "nsim" if SOC_NSIM

soc/snps/nsim/linker.ld

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Linker script for the Synopsys EM Starterkit platform.
+ */
+
+#include <zephyr/devicetree.h>
+
+/* Instruction Closely Coupled Memory (ICCM) base address and size */
+#if DT_NODE_HAS_PROP(DT_INST(0, arc_iccm), reg) && \
+    (DT_REG_SIZE(DT_INST(0, arc_iccm)) > 0)
+#define ICCM_START		DT_REG_ADDR(DT_INST(0, arc_iccm))
+#define ICCM_SIZE		DT_REG_SIZE(DT_INST(0, arc_iccm))
+#endif
+
+/*
+ * DCCM base address and size. DCCM is the data memory.
+ */
+/* Data Closely Coupled Memory (DCCM) base address and size */
+#if DT_NODE_HAS_PROP(DT_INST(0, arc_dccm), reg) && \
+    (DT_REG_SIZE(DT_INST(0, arc_dccm)) > 0)
+#define DCCM_START		DT_REG_ADDR(DT_INST(0, arc_dccm))
+#define DCCM_SIZE		DT_REG_SIZE(DT_INST(0, arc_dccm))
+#endif
+
+/* SRAM - memory available for all cores in cluster. Can be used for both instructions and data */
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
+#define SRAM_START		DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
+#define SRAM_SIZE		DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
+#endif
+
+/* Flash memory base address and size */
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_flash), reg) && \
+    (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
+#define FLASH_START		DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
+#define FLASH_SIZE		DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
+#endif
+
+
+#include <zephyr/arch/arc/v2/xy_mem.ld>
+#include <zephyr/arch/arc/v2/linker.ld>

soc/snps/nsim/soc.yml

@@ -0,0 +1,15 @@
+series:
+- name: nsim
+  socs:
+  - name: nsim_em
+  - name: nsim_em7d_v22
+  - name: nsim_em11d
+  - name: nsim_hs
+  - name: nsim_hs_smp
+  - name: nsim_hs_mpuv6
+  - name: nsim_hs5x
+  - name: nsim_hs5x_smp
+  - name: nsim_hs6x
+  - name: nsim_hs6x_smp
+  - name: nsim_vpx5
+  - name: nsim_sem

soc/snps/qemu_arc/CMakeLists.txt

@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(COMPILER STREQUAL gcc)
+  zephyr_compile_options(-mcpu=${GCC_M_CPU})
+
+  zephyr_compile_options_ifdef(CONFIG_ISA_ARCV2 -mno-sdata)
+else()
+  zephyr_compile_options_ifdef(CONFIG_SOC_QEMU_ARC_HS -arcv2hs -core2 -Xatomic
+                               -Xunaligned -Xcode_density -Xswap -Xbitscan
+                               -Xmpy_option=qmpyh -Xshift_assist -Xbarrel_shifter
+                               -Xtimer0 -Xtimer1)
+
+  zephyr_ld_option_ifdef(CONFIG_SOC_QEMU_ARC_HS -Hlib=hs38_full)
+
+  if(NOT CONFIG_SOC_QEMU_ARC_HS)
+    message(WARNING "QEMU ARC platforms other than HS3X are not supported yet with MW toolchain")
+  endif()
+endif()
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

soc/snps/qemu_arc/Kconfig

@@ -0,0 +1,18 @@
+# Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_ARC
+	select ARC
+	select CPU_HAS_MPU
+
+config SOC_QEMU_ARC_EM
+	select CPU_EM4
+
+config SOC_QEMU_ARC_HS
+	select CPU_HS3X
+
+config SOC_QEMU_ARC_HS5X
+	select CPU_HS5X
+
+config SOC_QEMU_ARC_HS6X
+	select CPU_HS6X

soc/snps/qemu_arc/Kconfig.defconfig

@@ -0,0 +1,29 @@
+# Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_QEMU_ARC
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 10000000
+
+config RGF_NUM_BANKS
+	default 1
+
+config ARC_FIRQ
+	default n
+
+config NUM_IRQ_PRIO_LEVELS
+	default 15
+
+config NUM_IRQS
+	default 26
+
+# Technically ARC HS supports MPUv3, but not v2. But given MPUv3
+# is the same as v2 but with minimal region size of 32 bytes, we
+# may assume MPUv3 is just a subset of MPUv2.
+
+config ARC_MPU_VER
+	default 2
+
+endif

soc/snps/qemu_arc/Kconfig.soc

@@ -0,0 +1,30 @@
+# Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_ARC
+	bool
+
+config SOC_QEMU_ARC_EM
+	bool
+	select SOC_QEMU_ARC
+
+config SOC_QEMU_ARC_HS
+	bool
+	select SOC_QEMU_ARC
+
+config SOC_QEMU_ARC_HS5X
+	bool
+	select SOC_QEMU_ARC
+
+config SOC_QEMU_ARC_HS6X
+	bool
+	select SOC_QEMU_ARC
+
+config SOC_SERIES
+	default "qemu_arc" if SOC_QEMU_ARC
+
+config SOC
+	default "qemu_arc_em" if SOC_QEMU_ARC_EM
+	default "qemu_arc_hs" if SOC_QEMU_ARC_HS
+	default "qemu_arc_hs5x" if SOC_QEMU_ARC_HS5X
+	default "qemu_arc_hs6x" if SOC_QEMU_ARC_HS6X

soc/snps/qemu_arc/linker.ld

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+
+/*
+ * SRAM base address and size
+ */
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
+    (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
+#define SRAM_START		DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
+#define SRAM_SIZE		DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
+#endif
+
+/*
+ * flash base address and size
+ */
+#if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_flash), reg) && \
+    (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
+#define FLASH_START		DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
+#define FLASH_SIZE		DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
+#endif
+
+#include <zephyr/arch/arc/v2/linker.ld>

soc/snps/qemu_arc/soc.yml

@@ -0,0 +1,7 @@
+series:
+- name: qemu_arc
+  socs:
+  - name: qemu_arc_em
+  - name: qemu_arc_hs
+  - name: qemu_arc_hs5x
+  - name: qemu_arc_hs6x