boards: ezurio: bl54l15_dvk: Add BL54L15/L15u DVK support

Adds support for the BL54L15 and BL54L15u DVK boards.

Signed-off-by: Greg Leach <greg.leach@ezurio.com>

boards/ezurio/bl54l15_dvk/Kconfig

@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# BL54L15 DVK board configuration
+
+if BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS
+
+DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc)
+
+config NRF_TRUSTZONE_FLASH_REGION_SIZE
+	hex
+	default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
+	help
+	  This defines the flash region size from the TrustZone perspective.
+	  It is used when configuring the TrustZone and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TrustZone without depending
+	  on peripheral-specific symbols.
+
+config NRF_TRUSTZONE_RAM_REGION_SIZE
+	hex
+	default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
+	help
+	  This defines the RAM region size from the TrustZone perspective.
+	  It is used when configuring the TrustZone and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TrustZone without depending
+	  on peripheral specific symbols.
+
+endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS

boards/ezurio/bl54l15_dvk/Kconfig.bl54l15_dvk

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BL54L15_DVK
+	select SOC_NRF54L10_CPUAPP if BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS
+	select SOC_NRF54L15_CPUAPP if BOARD_BL54L15_DVK_NRF54L15_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS
+	select SOC_NRF54L15_CPUFLPR if BOARD_BL54L15_DVK_NRF54L15_CPUFLPR || \
+					    BOARD_BL54L15_DVK_NRF54L15_CPUFLPR_XIP

boards/ezurio/bl54l15_dvk/Kconfig.defconfig

@@ -0,0 +1,32 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
+DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
+
+if BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP
+
+if BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS
+
+config BT_CTLR
+	default BT
+
+config FLASH_LOAD_OFFSET
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+# By default, if we build for a Non-Secure version of the board,
+# enable building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+	default y
+
+endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS

boards/ezurio/bl54l15_dvk/bl54l15_dvk_common.dtsi

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l_10_15-pinctrl.dtsi"
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 0";
+		};
+
+		led1: led_1 {
+			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 1";
+		};
+
+		led2: led_2 {
+			gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 2";
+		};
+
+		led3: led_3 {
+			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 3";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		/*
+		 * PWM signal can be exposed on GPIO pin only within same domain.
+		 * There is only one domain which contains both PWM and GPIO:
+		 * PWM20/21/22 and GPIO Port P1.
+		 * Only LEDs connected to P1 can work with PWM, for example LED1.
+		 */
+		pwm_led1: pwm_led_1 {
+			pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 0";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: button_1 {
+			gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 1";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+
+		button2: button_2 {
+			gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 2";
+			zephyr,code = <INPUT_KEY_2>;
+		};
+
+		button3: button_3 {
+			gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 3";
+			zephyr,code = <INPUT_KEY_3>;
+		};
+	};
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		led2 = &led2;
+		led3 = &led3;
+		pwm-led0 = &pwm_led1;
+		sw0 = &button0;
+		sw1 = &button1;
+		sw2 = &button2;
+		sw3 = &button3;
+		watchdog0 = &wdt31;
+	};
+};
+
+&uart20 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart20_default>;
+	pinctrl-1 = <&uart20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart30 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&pwm20 {
+	status = "okay";
+	pinctrl-0 = <&pwm20_default>;
+	pinctrl-1 = <&pwm20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+/* Get a node label for wi-fi spi to use in shield files */
+wifi_spi: &spi22 {};

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nordic/nrf54l10_cpuapp.dtsi>
+#include "nrf54l_10_15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15_dvk_nrf54l10-cpuapp";
+	model = "Ezurio BL54L15 DVK nRF54L10 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram = &cpuapp_sram;
+	};
+};
+
+/* FLPR not supported yet, give all SRAM and RRAM to the APP core */
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(192)>;
+	ranges = <0x0 0x20000000 DT_SIZE_K(192)>;
+};
+
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(1022)>;
+};
+
+/* These partition sizes assume no FLPR area in RRAM */
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(224)>;
+		};
+
+		slot0_ns_partition: partition@48000 {
+			label = "image-0-nonsecure";
+			reg = <0x48000 DT_SIZE_K(224)>;
+		};
+
+		slot1_partition: partition@80000 {
+			label = "image-1";
+			reg = <0x80000 DT_SIZE_K(224)>;
+		};
+
+		slot1_ns_partition: partition@b8000 {
+			label = "image-1-nonsecure";
+			reg = <0xb8000 DT_SIZE_K(224)>;
+		};
+
+		/* 32K from 0xf0000 to 0xf7fff reserved for TF-M partitions */
+
+		storage_partition: partition@f8000 {
+			label = "storage";
+			reg = <0xf8000 DT_SIZE_K(28)>;
+		};
+
+		/* 2K from 0xff000 to 0xff7ff unused */
+	};
+};

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.yaml

@@ -0,0 +1,24 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l10/cpuapp
+name: BL54L15-DVK-nRF54L10-Application
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 192
+flash: 230
+supported:
+  - adc
+  - counter
+  - gpio
+  - i2c
+  - pwm
+  - retained_mem
+  - spi
+  - watchdog
+  - i2s

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_defconfig

@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts

@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#define USE_NON_SECURE_ADDRESS_MAP 1
+
+#include <nordic/nrf54l10_cpuapp.dtsi>
+#include "nrf54l_10_15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15_dvk_nrf54l10-cpuapp";
+	model = "Ezurio BL54L15 DVK nRF54L10 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_ns_partition;
+		zephyr,sram = &sram0_ns;
+		zephyr,entropy = &psa_rng;
+	};
+
+	/delete-node/ rng;
+
+	psa_rng: psa-rng {
+		status = "okay";
+	};
+};
+
+/ {
+	/*
+	 * Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support.
+	 * - Lowest 96 kB SRAM allocated to Secure image (sram0_s).
+	 * - Upper 96 kB SRAM allocated to Non-Secure image (sram0_ns).
+	 *
+	 * nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for
+	 * the FLPR MCU.
+	 * This static layout needs to be the same with the upstream TF-M layout in the
+	 * header flash_layout.h of the relevant platform. Any updates in the layout
+	 * needs to happen both in the flash_layout.h and in this file at the same time.
+	 */
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram0_s: image_s@20000000 {
+			/* Secure image memory */
+			reg = <0x20000000 DT_SIZE_K(72)>;
+		};
+
+		sram0_ns: image_ns@20012000 {
+			/* Non-Secure image memory */
+			reg = <0x20012000 DT_SIZE_K(72)>;
+		};
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		/* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the
+		 * last 62kB are reserved for the FLPR MCU.
+		 *
+		 * This static layout needs to be the same with the upstream TF-M layout in the
+		 * header flash_layout.h of the relevant platform. Any updates in the layout
+		 * needs to happen both in the flash_layout.h and in this file at the same time.
+		 */
+		slot0_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0000000 DT_SIZE_K(384)>;
+		};
+
+		tfm_ps_partition: partition@60000 {
+			label = "tfm-ps";
+			reg = <0x00060000 DT_SIZE_K(16)>;
+		};
+
+		tfm_its_partition: partition@64000 {
+			label = "tfm-its";
+			reg = <0x00064000 DT_SIZE_K(16)>;
+		};
+
+		tfm_otp_partition: partition@68000 {
+			label = "tfm-otp";
+			reg = <0x00068000 DT_SIZE_K(8)>;
+		};
+
+		slot0_ns_partition: partition@6A000 {
+			label = "image-0-nonsecure";
+			reg = <0x0006A000 DT_SIZE_K(504)>;
+		};
+
+		storage_partition: partition@E8000 {
+			label = "storage";
+			reg = <0x000E8000 DT_SIZE_K(32)>;
+		};
+	};
+};
+
+&uart30 {
+	/* Disable so that TF-M can use this UART */
+	status = "disabled";
+};

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml

@@ -0,0 +1,23 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l10/cpuapp/ns
+name: BL54L15-DVK-nRF54l10-Application-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 192
+flash: 1022
+supported:
+  - adc
+  - gpio
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - adc
+  - i2s

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns_defconfig

@@ -0,0 +1,37 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# Don't enable the cache in the non-secure image as it is a
+# secure-only peripheral on 54l
+CONFIG_CACHE_MANAGEMENT=n
+CONFIG_EXTERNAL_CACHE=n
+
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y
+
+# Disable TFM BL2 since it is not supported
+CONFIG_TFM_BL2=n
+
+# Support for silence logging is not supported at the moment
+# Tracked by: NCSDK-31930
+CONFIG_TFM_LOG_LEVEL_SILENCE=n
+
+# The oscillators are configured as secure and cannot be configured
+# from the non secure application directly. This needs to be set
+# otherwise nrfx will try to configure them, resulting in a bus
+# fault.
+CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.dts

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nordic/nrf54l15_cpuapp.dtsi>
+#include "nrf54l_10_15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15_dvk_nrf54l15-cpuapp";
+	model = "Ezurio BL54L15_DVK nRF54L15 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram = &cpuapp_sram;
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(324)>;
+		};
+
+		slot0_ns_partition: partition@61000 {
+			label = "image-0-nonsecure";
+			reg = <0x61000 DT_SIZE_K(324)>;
+		};
+
+		slot1_partition: partition@b2000 {
+			label = "image-1";
+			reg = <0xb2000 DT_SIZE_K(324)>;
+		};
+
+		slot1_ns_partition: partition@103000 {
+			label = "image-1-nonsecure";
+			reg = <0x103000 DT_SIZE_K(324)>;
+		};
+
+		/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
+		storage_partition: partition@15c000 {
+			label = "storage";
+			reg = <0x15c000 DT_SIZE_K(36)>;
+		};
+	};
+};

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.yaml

@@ -0,0 +1,25 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l15/cpuapp
+name: BL54L15-DVK-nRF54l15-Application
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 188
+flash: 324
+supported:
+  - adc
+  - counter
+  - dmic
+  - gpio
+  - i2c
+  - pwm
+  - retained_mem
+  - spi
+  - watchdog
+  - i2s

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_defconfig

@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts

@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#define USE_NON_SECURE_ADDRESS_MAP 1
+
+#include <nordic/nrf54l15_cpuapp.dtsi>
+#include "nrf54l_10_15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15_dvk_nrf54l15-cpuapp";
+	model = "Ezurio BL54L15 DVK nRF54L15 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_ns_partition;
+		zephyr,sram = &sram0_ns;
+		zephyr,entropy = &psa_rng;
+	};
+
+	/delete-node/ rng;
+
+	psa_rng: psa-rng {
+		status = "okay";
+	};
+};
+
+/ {
+	/*
+	 * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support
+	 * - Lowest 80 kB SRAM allocated to Secure image (sram0_s).
+	 * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns).
+	 *
+	 * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for
+	 * the FLPR MCU.
+	 * This static layout needs to be the same with the upstream TF-M layout in the
+	 * header flash_layout.h of the relevant platform. Any updates in the layout
+	 * needs to happen both in the flash_layout.h and in this file at the same time.
+	 */
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram0_s: image_s@20000000 {
+			/* Secure image memory */
+			reg = <0x20000000 DT_SIZE_K(80)>;
+		};
+
+		sram0_ns: image_ns@20014000 {
+			/* Non-Secure image memory */
+			reg = <0x20014000 DT_SIZE_K(80)>;
+		};
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the
+		 * last 96kB are reserved for the FLPR MCU.
+		 *
+		 * This static layout needs to be the same with the upstream TF-M layout in the
+		 * header flash_layout.h of the relevant platform. Any updates in the layout
+		 * needs to happen both in the flash_layout.h and in this file at the same time.
+		 */
+		slot0_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0000000 DT_SIZE_K(512)>;
+		};
+
+		tfm_ps_partition: partition@80000 {
+			label = "tfm-ps";
+			reg = <0x00080000 DT_SIZE_K(16)>;
+		};
+
+		tfm_its_partition: partition@84000 {
+			label = "tfm-its";
+			reg = <0x00084000 DT_SIZE_K(16)>;
+		};
+
+		tfm_otp_partition: partition@88000 {
+			label = "tfm-otp";
+			reg = <0x00088000 DT_SIZE_K(8)>;
+		};
+
+		slot0_ns_partition: partition@8A000 {
+			label = "image-0-nonsecure";
+			reg = <0x0008A000 DT_SIZE_K(844)>;
+		};
+
+		storage_partition: partition@15D000 {
+			label = "storage";
+			reg = <0x00015D000 DT_SIZE_K(32)>;
+		};
+	};
+};
+
+&uart30 {
+	/* Disable so that TF-M can use this UART */
+	status = "disabled";
+
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.yaml

@@ -0,0 +1,23 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l15/cpuapp/ns
+name: BL54L15-DVK-nRF54l15-Application-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 256
+flash: 1524
+supported:
+  - adc
+  - gpio
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - adc
+  - i2s

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns_defconfig

@@ -0,0 +1,37 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# Don't enable the cache in the non-secure image as it is a
+# secure-only peripheral on 54l
+CONFIG_CACHE_MANAGEMENT=n
+CONFIG_EXTERNAL_CACHE=n
+
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y
+
+# Disable TFM BL2 since it is not supported
+CONFIG_TFM_BL2=n
+
+# Support for silence logging is not supported at the moment
+# Tracked by: NCSDK-31930
+CONFIG_TFM_LOG_LEVEL_SILENCE=n
+
+# The oscillators are configured as secure and cannot be configured
+# from the non secure application directly. This needs to be set
+# otherwise nrfx will try to configure them, resulting in a bus
+# fault.
+CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.dts

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf54l15_cpuflpr.dtsi>
+#include "bl54l15_dvk_common.dtsi"
+
+/ {
+	model = "Ezurio BL54L15 DVK nRF54L15 FLPR MCU";
+	compatible = "ezurio,bl54l15_dvk_nrf54l15-cpuflpr";
+
+	chosen {
+		zephyr,console = &uart30;
+		zephyr,shell-uart = &uart30;
+		zephyr,code-partition = &cpuflpr_code_partition;
+		zephyr,flash = &cpuflpr_rram;
+		zephyr,sram = &cpuflpr_sram;
+	};
+};
+
+&cpuflpr_sram {
+	status = "okay";
+	/* size must be increased due to booting from SRAM */
+	reg = <0x20028000 DT_SIZE_K(96)>;
+	ranges = <0x0 0x20028000 0x18000>;
+};
+
+&cpuflpr_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuflpr_code_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0 DT_SIZE_K(96)>;
+		};
+	};
+};
+
+&grtc {
+	owned-channels = <3 4>;
+	status = "okay";
+};
+
+&uart30 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.yaml

@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l15/cpuflpr
+name: BL54L15-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 96
+flash: 96
+supported:
+  - counter
+  - gpio
+  - i2c
+  - spi
+  - watchdog

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_defconfig

@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Execute from SRAM
+CONFIG_XIP=n

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.dts

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_cpuflpr.dts"
+
+&cpuflpr_sram {
+	reg = <0x2002f000 DT_SIZE_K(68)>;
+	ranges = <0x0 0x2002f000 0x11000>;
+};

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.yaml

@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l15/cpuflpr/xip
+name: BL54L15-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP)
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 68
+flash: 96
+supported:
+  - counter
+  - gpio
+  - i2c
+  - spi
+  - watchdog

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip_defconfig

@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Execute from RRAM
+CONFIG_XIP=y

boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l_10_15-pinctrl.dtsi

@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	/omit-if-no-ref/ uart20_default: uart20_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RTS, 1, 6)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 1, 5)>,
+				<NRF_PSEL(UART_CTS, 1, 7)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart20_sleep: uart20_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RX, 1, 5)>,
+				<NRF_PSEL(UART_RTS, 1, 6)>,
+				<NRF_PSEL(UART_CTS, 1, 7)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_default: uart30_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_sleep: uart30_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_default: spi00_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_sleep: spi00_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+				low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_default: pwm20_default {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_default: grtc_default {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_sleep: grtc_sleep {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+			low-power-enable;
+		};
+	};
+};

boards/ezurio/bl54l15_dvk/board.cmake

@@ -0,0 +1,23 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_NRF54L10_CPUAPP OR CONFIG_SOC_NRF54L15_CPUAPP)
+  board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000")
+elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
+  board_runner_args(jlink "--device=nRF54L15_RV32")
+elseif(CONFIG_SOC_NRF54L10_CPUFLPR)
+  set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54l_10_15_cpuflpr.JLinkScript)
+  board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}")
+endif()
+
+if(CONFIG_BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS OR CONFIG_BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS)
+  set(TFM_PUBLIC_KEY_FORMAT "full")
+endif()
+
+if(CONFIG_TFM_FLASH_MERGED_BINARY)
+  set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/ezurio/bl54l15_dvk/board.yml

@@ -0,0 +1,52 @@
+board:
+  name: bl54l15_dvk
+  full_name: BL54L15 DVK
+  vendor: ezurio
+  socs:
+    - name: nrf54l10
+      variants:
+        - name: ns
+          cpucluster: cpuapp
+    - name: nrf54l15
+      variants:
+        - name: xip
+          cpucluster: cpuflpr
+        - name: ns
+          cpucluster: cpuapp
+runners:
+  run_once:
+    '--recover':
+      - runners:
+          - nrfjprog
+          - nrfutil
+        run: first
+        groups:
+          - boards:
+              - bl54l15_dvk/nrf54l15/cpuapp
+              - bl54l15_dvk/nrf54l15/cpuapp/ns
+              - bl54l15_dvk/nrf54l15/cpuflpr
+              - bl54l15_dvk/nrf54l15/cpuflpr/xip
+    '--erase':
+      - runners:
+          - nrfjprog
+          - jlink
+          - nrfutil
+        run: first
+        groups:
+          - boards:
+              - bl54l15_dvk/nrf54l15/cpuapp
+              - bl54l15_dvk/nrf54l15/cpuapp/ns
+              - bl54l15_dvk/nrf54l15/cpuflpr
+              - bl54l15_dvk/nrf54l15/cpuflpr/xip
+    '--reset':
+      - runners:
+          - nrfjprog
+          - jlink
+          - nrfutil
+        run: last
+        groups:
+          - boards:
+              - bl54l15_dvk/nrf54l15/cpuapp
+              - bl54l15_dvk/nrf54l15/cpuapp/ns
+              - bl54l15_dvk/nrf54l15/cpuflpr
+              - bl54l15_dvk/nrf54l15/cpuflpr/xip

boards/ezurio/bl54l15_dvk/doc/bl54l15_dvk.rst

@@ -0,0 +1,142 @@
+.. zephyr:board:: bl54l15_dvk
+
+Overview
+********
+
+.. note::
+   You can find more information about the BL54L15 module on the `BL54L15 website`_.
+
+   You can find more information about the BL54L10 module on the `BL54L10 website`_.
+
+   You can find more information about the underlying nRF54L15 SoC on the
+   `nRF54L15 website`_. For the nRF54L15 technical documentation and other
+   resources (such as SoC Datasheet), see the `nRF54L15 documentation`_ page.
+
+The BL54L15 Development Kit provides support for the Ezurio BL54L15 and BL54L10
+range of modules.
+
+The modules are based on the Nordic Semiconductor nRF54L15 and nRF54L10 Arm Cortex-M33 CPUs.
+
+The BL54L15 module incorporates the QFN package nRF54L15 (1524kB Flash, 256kB RAM). The BL54L10
+module the QFN package nRF54L10 (1022kB Flash, 192kB RAM). Both parts feature up to 31 configurable
+GPIOs and BLE Radio TX Power up to 7dBm.
+
+The modules include the following devices:
+
+* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)`
+* CLOCK
+* RRAM
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
+* MEMCONF
+* :abbr:`MPU (Memory Protection Unit)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+* :abbr:`PWM (Pulse Width Modulation)`
+* :abbr:`GRTC (Global real-time counter)`
+* Segger RTT (RTT Console)
+* :abbr:`SPI (Serial Peripheral Interface)`
+* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
+* :abbr:`WDT (Watchdog Timer)`
+
+Hardware
+********
+
+The BL54L15 DVK has two crystal oscillators:
+
+* High-frequency 32 MHz crystal oscillator (HFXO)
+* Low-frequency 32.768 kHz crystal oscillator (LFXO)
+
+The crystal oscillators can be configured to use either
+internal or external capacitors.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+Applications for the ``bl54l15_dvk/nrf54l15/cpuapp`` and ``bl54l15_dvk/nrf54l10/cpuapp``
+board targets can be built, flashed, and debugged in the usual way.
+See :ref:`build_an_application` and :ref:`application_run` for more
+details on building and running.
+
+Applications for the ``bl54l15_dvk/nrf54l15/cpuflpr`` board target need to be built
+using sysbuild to include the ``vpr_launcher`` image for the application core.
+
+Enter the following command to compile ``hello_world`` for the FLPR core:
+
+.. code-block:: console
+
+   west build -p -b bl54l15_dvk/nrf54l15/cpuflpr --sysbuild
+
+Flashing
+========
+
+As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
+application.
+
+.. warning::
+
+   When programming the device, you might get an error similar to the following message::
+
+    ERROR: The operation attempted is unavailable due to readback protection in
+    ERROR: your device. Please use --recover to unlock the device.
+
+   This error occurs when readback protection is enabled.
+   To disable the readback protection, you must *recover* your device.
+
+   Enter the following command to recover the core::
+
+    west flash --recover
+
+   The ``--recover`` command erases the flash memory and then writes a small binary into
+   the recovered flash memory.
+   This binary prevents the readback protection from enabling itself again after a pin
+   reset or power cycle.
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`.
+
+To build and program the sample to the BL54L15 DVK, complete the following steps:
+
+First, connect the BL54L15 DVK to your computer using the IMCU USB port on the DVK.
+Next, build the sample by running the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: bl54l15_dvk/nrf54l15/cpuapp
+   :goals: build flash
+
+Testing the LEDs and buttons on the BL54L15 DVK
+************************************************
+
+Test the BL54L15 DVK with a :zephyr:code-sample:`blinky` sample.
+
+.. _BL54L15 website: https://www.ezurio.com/product/bl54l15-series-bluetooth-le-80215-4-nfc
+.. _BL54L10 website: https://www.ezurio.com/wireless-modules/bluetooth-modules/bl54-series/bl54l10-series-bluetooth-le-802-15-4-nfc
+.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15
+.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html
+
+.. _bl54l15_dvk_nrf54l10:
+
+BL54L10 emulation on BL54L15 DVK
+********************************
+
+Overview
+========
+
+The ``bl54l15_dvk/nrf54l10`` board is a modified version of the BL54L15 DVK
+that enforces the limitations imposed by the nRF54L10 IC, upon which the BL54L10 is based.
+The nRF54L10 is a cost-reduced variant of the original nRF54L15. Since Ezurio does not offer a
+development kit for the BL54L10 you can use this board to develop for this
+module while using the BL54L15 Development Kit (453-00001-K1, 453-00044-K1).
+
+See above for more information about the development board. Refer to
+the `BL54L10 website`_ for details of the BL54L10 module and the `nRF54L10 website`_ for
+the official reference on the underlying SoC.
+
+.. _BL54L10 website: https://www.ezurio.com/wireless-modules/bluetooth-modules/bl54-series/bl54l10-series-bluetooth-le-802-15-4-nfc
+.. _nRF54L10 website: https://www.nordicsemi.com/Products/nRF54L10

boards/ezurio/bl54l15_dvk/nrf54l_10_15_cpuapp_common.dtsi

@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is common to the secure and non-secure domain */
+
+#include "bl54l15_dvk_common.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+		zephyr,shell-uart = &uart20;
+		zephyr,uart-mcumgr = &uart20;
+		zephyr,bt-mon-uart = &uart20;
+		zephyr,bt-c2h-uart = &uart20;
+		zephyr,flash-controller = &rram_controller;
+		zephyr,flash = &cpuapp_rram;
+		zephyr,ieee802154 = &ieee802154;
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+};
+
+&lfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15500>;
+};
+
+&hfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15000>;
+};
+
+&regulators {
+	status = "okay";
+};
+
+&vregmain {
+	status = "okay";
+	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&uart20 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&clock {
+	status = "okay";
+};
+
+&spi00 {
+	status = "okay";
+	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	mx25r64: mx25r6435f@0 {
+		compatible = "jedec,spi-nor";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <8000000>;
+		jedec-id = [c2 28 17];
+		sfdp-bfp = [
+			e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
+			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
+			10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 48 44
+			30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
+		];
+		size = <67108864>;
+		has-dpd;
+		t-enter-dpd = <10000>;
+		t-exit-dpd = <35000>;
+	};
+};
+
+&adc {
+	status = "okay";
+};

boards/ezurio/bl54l15_dvk/support/nrf54l_10_15_cpuflpr.JLinkScript

@@ -0,0 +1,5 @@
+int InitTarget(void) {
+  // Base address where DMI registers can be found in the APB address space
+  JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x5004C400");
+  return 0;
+}

boards/ezurio/bl54l15u_dvk/Kconfig

@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# BL54L15U DVK board configuration
+
+if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS
+
+DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc)
+
+config NRF_TRUSTZONE_FLASH_REGION_SIZE
+	hex
+	default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
+	help
+	  This defines the flash region size from the TrustZone perspective.
+	  It is used when configuring the TrustZone and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TrustZone without depending
+	  on peripheral-specific symbols.
+
+config NRF_TRUSTZONE_RAM_REGION_SIZE
+	hex
+	default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
+	help
+	  This defines the RAM region size from the TrustZone perspective.
+	  It is used when configuring the TrustZone and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TrustZone without depending
+	  on peripheral specific symbols.
+
+endif # BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS

boards/ezurio/bl54l15u_dvk/Kconfig.bl54l15u_dvk

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BL54L15U_DVK
+	select SOC_NRF54L15_CPUAPP if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP || BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS
+	select SOC_NRF54L15_CPUFLPR if BOARD_BL54L15U_DVK_NRF54L15_CPUFLPR || \
+					    BOARD_BL54L15U_DVK_NRF54L15_CPUFLPR_XIP

boards/ezurio/bl54l15u_dvk/Kconfig.defconfig

@@ -0,0 +1,32 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
+DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
+
+if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+endif # BOARD_BL54L15U_DVK_NRF54L15_CPUAPP
+
+if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS
+
+config BT_CTLR
+	default BT
+
+config FLASH_LOAD_OFFSET
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+# By default, if we build for a Non-Secure version of the board,
+# enable building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+	default y
+
+endif # BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_common.dtsi

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15u_dvk_nrf54l15-pinctrl.dtsi"
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 0";
+		};
+
+		led1: led_1 {
+			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 1";
+		};
+
+		led2: led_2 {
+			gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 2";
+		};
+
+		led3: led_3 {
+			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 3";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		/*
+		 * PWM signal can be exposed on GPIO pin only within same domain.
+		 * There is only one domain which contains both PWM and GPIO:
+		 * PWM20/21/22 and GPIO Port P1.
+		 * Only LEDs connected to P1 can work with PWM, for example LED1.
+		 */
+		pwm_led1: pwm_led_1 {
+			pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 0";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: button_1 {
+			gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 1";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+
+		button2: button_2 {
+			gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 2";
+			zephyr,code = <INPUT_KEY_2>;
+		};
+
+		button3: button_3 {
+			gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 3";
+			zephyr,code = <INPUT_KEY_3>;
+		};
+	};
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		led2 = &led2;
+		led3 = &led3;
+		pwm-led0 = &pwm_led1;
+		sw0 = &button0;
+		sw1 = &button1;
+		sw2 = &button2;
+		sw3 = &button3;
+		watchdog0 = &wdt31;
+	};
+};
+
+&uart20 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart20_default>;
+	pinctrl-1 = <&uart20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart30 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&pwm20 {
+	status = "okay";
+	pinctrl-0 = <&pwm20_default>;
+	pinctrl-1 = <&pwm20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+/* Get a node label for wi-fi spi to use in shield files */
+wifi_spi: &spi22 {};

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15-pinctrl.dtsi

@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	/omit-if-no-ref/ uart20_default: uart20_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RTS, 1, 6)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 1, 5)>,
+				<NRF_PSEL(UART_CTS, 1, 7)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart20_sleep: uart20_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RX, 1, 5)>,
+				<NRF_PSEL(UART_RTS, 1, 6)>,
+				<NRF_PSEL(UART_CTS, 1, 7)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_default: uart30_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_sleep: uart30_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_default: spi00_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_sleep: spi00_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+				low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_default: pwm20_default {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_default: grtc_default {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_sleep: grtc_sleep {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+			low-power-enable;
+		};
+	};
+};

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.dts

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nordic/nrf54l15_cpuapp.dtsi>
+#include "nrf54l15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15u_dvk_nrf54l15-cpuapp";
+	model = "Ezurio BL54L15u_DVK nRF54L15 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram = &cpuapp_sram;
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(324)>;
+		};
+
+		slot0_ns_partition: partition@61000 {
+			label = "image-0-nonsecure";
+			reg = <0x61000 DT_SIZE_K(324)>;
+		};
+
+		slot1_partition: partition@b2000 {
+			label = "image-1";
+			reg = <0xb2000 DT_SIZE_K(324)>;
+		};
+
+		slot1_ns_partition: partition@103000 {
+			label = "image-1-nonsecure";
+			reg = <0x103000 DT_SIZE_K(324)>;
+		};
+
+		/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
+		storage_partition: partition@15c000 {
+			label = "storage";
+			reg = <0x15c000 DT_SIZE_K(36)>;
+		};
+	};
+};

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.yaml

@@ -0,0 +1,25 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15u_dvk/nrf54l15/cpuapp
+name: BL54L15u-DVK-nRF54l15-Application
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 188
+flash: 324
+supported:
+  - adc
+  - counter
+  - dmic
+  - gpio
+  - i2c
+  - pwm
+  - retained_mem
+  - spi
+  - watchdog
+  - i2s

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_defconfig

@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts

@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#define USE_NON_SECURE_ADDRESS_MAP 1
+
+#include <nordic/nrf54l15_cpuapp.dtsi>
+#include "nrf54l15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15u_dvk_nrf54l15-cpuapp";
+	model = "Ezurio BL54L15u DVK nRF54L15 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_ns_partition;
+		zephyr,sram = &sram0_ns;
+		zephyr,entropy = &psa_rng;
+	};
+
+	/delete-node/ rng;
+
+	psa_rng: psa-rng {
+		status = "okay";
+	};
+};
+
+/ {
+	/*
+	 * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support
+	 * - Lowest 80 kB SRAM allocated to Secure image (sram0_s).
+	 * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns).
+	 *
+	 * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for
+	 * the FLPR MCU.
+	 * This static layout needs to be the same with the upstream TF-M layout in the
+	 * header flash_layout.h of the relevant platform. Any updates in the layout
+	 * needs to happen both in the flash_layout.h and in this file at the same time.
+	 */
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram0_s: image_s@20000000 {
+			/* Secure image memory */
+			reg = <0x20000000 DT_SIZE_K(80)>;
+		};
+
+		sram0_ns: image_ns@20014000 {
+			/* Non-Secure image memory */
+			reg = <0x20014000 DT_SIZE_K(80)>;
+		};
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the
+		 * last 96kB are reserved for the FLPR MCU.
+		 *
+		 * This static layout needs to be the same with the upstream TF-M layout in the
+		 * header flash_layout.h of the relevant platform. Any updates in the layout
+		 * needs to happen both in the flash_layout.h and in this file at the same time.
+		 */
+		slot0_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0000000 DT_SIZE_K(512)>;
+		};
+
+		tfm_ps_partition: partition@80000 {
+			label = "tfm-ps";
+			reg = <0x00080000 DT_SIZE_K(16)>;
+		};
+
+		tfm_its_partition: partition@84000 {
+			label = "tfm-its";
+			reg = <0x00084000 DT_SIZE_K(16)>;
+		};
+
+		tfm_otp_partition: partition@88000 {
+			label = "tfm-otp";
+			reg = <0x00088000 DT_SIZE_K(8)>;
+		};
+
+		slot0_ns_partition: partition@8A000 {
+			label = "image-0-nonsecure";
+			reg = <0x0008A000 DT_SIZE_K(844)>;
+		};
+
+		storage_partition: partition@15D000 {
+			label = "storage";
+			reg = <0x00015D000 DT_SIZE_K(32)>;
+		};
+	};
+};
+
+&uart30 {
+	/* Disable so that TF-M can use this UART */
+	status = "disabled";
+
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.yaml

@@ -0,0 +1,23 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+identifier: bl54l15u_dvk/nrf54l15/cpuapp/ns
+name: BL54L15u-DVK-nRF54l15-Application-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 256
+flash: 1524
+supported:
+  - adc
+  - gpio
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - adc
+  - i2s

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns_defconfig

@@ -0,0 +1,37 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# Don't enable the cache in the non-secure image as it is a
+# secure-only peripheral on 54l
+CONFIG_CACHE_MANAGEMENT=n
+CONFIG_EXTERNAL_CACHE=n
+
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y
+
+# Disable TFM BL2 since it is not supported
+CONFIG_TFM_BL2=n
+
+# Support for silence logging is not supported at the moment
+# Tracked by: NCSDK-31930
+CONFIG_TFM_LOG_LEVEL_SILENCE=n
+
+# The oscillators are configured as secure and cannot be configured
+# from the non secure application directly. This needs to be set
+# otherwise nrfx will try to configure them, resulting in a bus
+# fault.
+CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.dts

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf54l15_cpuflpr.dtsi>
+#include "bl54l15u_dvk_common.dtsi"
+
+/ {
+	model = "Ezurio BL54L15u DVK nRF54L15 FLPR MCU";
+	compatible = "ezurio,bl54l15u_dvk_nrf54l15-cpuflpr";
+
+	chosen {
+		zephyr,console = &uart30;
+		zephyr,shell-uart = &uart30;
+		zephyr,code-partition = &cpuflpr_code_partition;
+		zephyr,flash = &cpuflpr_rram;
+		zephyr,sram = &cpuflpr_sram;
+	};
+};
+
+&cpuflpr_sram {
+	status = "okay";
+	/* size must be increased due to booting from SRAM */
+	reg = <0x20028000 DT_SIZE_K(96)>;
+	ranges = <0x0 0x20028000 0x18000>;
+};
+
+&cpuflpr_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuflpr_code_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0 DT_SIZE_K(96)>;
+		};
+	};
+};
+
+&grtc {
+	owned-channels = <3 4>;
+	status = "okay";
+};
+
+&uart30 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.yaml

@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15u_dvk/nrf54l15/cpuflpr
+name: BL54L15u-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 96
+flash: 96
+supported:
+  - counter
+  - gpio
+  - i2c
+  - spi
+  - watchdog

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_defconfig

@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Execute from SRAM
+CONFIG_XIP=n

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.dts

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15u_dvk_nrf54l15_cpuflpr.dts"
+
+&cpuflpr_sram {
+	reg = <0x2002f000 DT_SIZE_K(68)>;
+	ranges = <0x0 0x2002f000 0x11000>;
+};

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.yaml

@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15u_dvk/nrf54l15/cpuflpr/xip
+name: BL54L15u-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP)
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 68
+flash: 96
+supported:
+  - counter
+  - gpio
+  - i2c
+  - spi
+  - watchdog

boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip_defconfig

@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Execute from RRAM
+CONFIG_XIP=y

boards/ezurio/bl54l15u_dvk/board.cmake

@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_NRF54L15_CPUAPP)
+  board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000")
+elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
+  board_runner_args(jlink "--device=nRF54L15_RV32")
+endif()
+
+if(CONFIG_BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS)
+  set(TFM_PUBLIC_KEY_FORMAT "full")
+endif()
+
+if(CONFIG_TFM_FLASH_MERGED_BINARY)
+  set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/ezurio/bl54l15u_dvk/board.yml

@@ -0,0 +1,48 @@
+board:
+  name: bl54l15u_dvk
+  full_name: BL54L15u DVK
+  vendor: ezurio
+  socs:
+    - name: nrf54l15
+      variants:
+        - name: xip
+          cpucluster: cpuflpr
+        - name: ns
+          cpucluster: cpuapp
+runners:
+  run_once:
+    '--recover':
+      - runners:
+          - nrfjprog
+          - nrfutil
+        run: first
+        groups:
+          - boards:
+              - bl54l15u_dvk/nrf54l15/cpuapp
+              - bl54l15u_dvk/nrf54l15/cpuapp/ns
+              - bl54l15u_dvk/nrf54l15/cpuflpr
+              - bl54l15u_dvk/nrf54l15/cpuflpr/xip
+    '--erase':
+      - runners:
+          - nrfjprog
+          - jlink
+          - nrfutil
+        run: first
+        groups:
+          - boards:
+              - bl54l15u_dvk/nrf54l15/cpuapp
+              - bl54l15u_dvk/nrf54l15/cpuapp/ns
+              - bl54l15u_dvk/nrf54l15/cpuflpr
+              - bl54l15u_dvk/nrf54l15/cpuflpr/xip
+    '--reset':
+      - runners:
+          - nrfjprog
+          - jlink
+          - nrfutil
+        run: last
+        groups:
+          - boards:
+              - bl54l15u_dvk/nrf54l15/cpuapp
+              - bl54l15u_dvk/nrf54l15/cpuapp/ns
+              - bl54l15u_dvk/nrf54l15/cpuflpr
+              - bl54l15u_dvk/nrf54l15/cpuflpr/xip

boards/ezurio/bl54l15u_dvk/doc/bl54l15u_dvk.rst

@@ -0,0 +1,115 @@
+.. zephyr:board:: bl54l15u_dvk
+
+Overview
+********
+
+.. note::
+   You can find more information about the BL54L15u module on the `BL54L15u website`_.
+
+   You can find more information about the underlying nRF54L15 SoC on the
+   `nRF54L15 website`_. For the nRF54L15 technical documentation and other
+   resources (such as SoC Datasheet), see the `nRF54L15 documentation`_ page.
+
+The BL54L15u Development Kit provides support for the Ezurio BL54L15u module.
+
+The module is based on the Nordic Semiconductor nRF54L15 Arm Cortex-M33 CPU.
+
+The BL54L15u module incorporates the WLCSP package nRF54L15 (1524kB Flash, 256kB RAM).
+The part features up to 32 configurable GPIOs and BLE Radio TX Power up to 8dBm.
+
+The module includes the following devices:
+
+* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)`
+* CLOCK
+* RRAM
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
+* MEMCONF
+* :abbr:`MPU (Memory Protection Unit)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+* :abbr:`PWM (Pulse Width Modulation)`
+* :abbr:`GRTC (Global real-time counter)`
+* Segger RTT (RTT Console)
+* :abbr:`SPI (Serial Peripheral Interface)`
+* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
+* :abbr:`WDT (Watchdog Timer)`
+
+Hardware
+********
+
+The BL54L15u DVK has two crystal oscillators:
+
+* High-frequency 32 MHz crystal oscillator (HFXO)
+* Low-frequency 32.768 kHz crystal oscillator (LFXO)
+
+The crystal oscillators can be configured to use either
+internal or external capacitors.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+Applications for the ``bl54l15u_dvk/nrf54l15/cpuapp`` board target can be built,
+flashed, and debugged in the usual way. See :ref:`build_an_application` and
+:ref:`application_run` for more details on building and running.
+
+Applications for the ``bl54l15u_dvk/nrf54l15/cpuflpr`` board target need to be
+built using sysbuild to include the ``vpr_launcher`` image for the application core.
+
+Enter the following command to compile ``hello_world`` for the FLPR core:
+
+.. code-block:: console
+
+   west build -p -b bl54l15u_dvk/nrf54l15/cpuflpr --sysbuild
+
+Flashing
+========
+
+As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
+application.
+
+.. warning::
+
+   When programming the device, you might get an error similar to the following message::
+
+    ERROR: The operation attempted is unavailable due to readback protection in
+    ERROR: your device. Please use --recover to unlock the device.
+
+   This error occurs when readback protection is enabled.
+   To disable the readback protection, you must *recover* your device.
+
+   Enter the following command to recover the core::
+
+    west flash --recover
+
+   The ``--recover`` command erases the flash memory and then writes a small binary into
+   the recovered flash memory.
+   This binary prevents the readback protection from enabling itself again after a pin
+   reset or power cycle.
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`.
+
+To build and program the sample to the BL54L15u DVK, complete the following steps:
+
+First, connect the BL54L15u DVK to your computer using the IMCU USB port on the DVK.
+Next, build the sample by running the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: bl54l15u_dvk/nrf54l15/cpuapp
+   :goals: build flash
+
+Testing the LEDs and buttons on the BL54L15u DVK
+************************************************
+
+Test the BL54L15u DVK with a :zephyr:code-sample:`blinky` sample.
+
+.. _BL54L15u website: https://www.ezurio.com/wireless-modules/bluetooth-modules/bl54-series/bl54l15-micro-series-bluetooth-le-802-15-4-nfc
+.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15
+.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html

boards/ezurio/bl54l15u_dvk/nrf54l15_cpuapp_common.dtsi

@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is common to the secure and non-secure domain */
+
+#include "bl54l15u_dvk_common.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+		zephyr,shell-uart = &uart20;
+		zephyr,uart-mcumgr = &uart20;
+		zephyr,bt-mon-uart = &uart20;
+		zephyr,bt-c2h-uart = &uart20;
+		zephyr,flash-controller = &rram_controller;
+		zephyr,flash = &cpuapp_rram;
+		zephyr,ieee802154 = &ieee802154;
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+};
+
+&lfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15500>;
+};
+
+&hfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15000>;
+};
+
+&regulators {
+	status = "okay";
+};
+
+&vregmain {
+	status = "okay";
+	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&uart20 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&clock {
+	status = "okay";
+};
+
+&spi00 {
+	status = "okay";
+	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	mx25r64: mx25r6435f@0 {
+		compatible = "jedec,spi-nor";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <8000000>;
+		jedec-id = [c2 28 17];
+		sfdp-bfp = [
+			e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
+			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
+			10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 48 44
+			30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
+		];
+		size = <67108864>;
+		has-dpd;
+		t-enter-dpd = <10000>;
+		t-exit-dpd = <35000>;
+	};
+};
+
+&adc {
+	status = "okay";
+};

boards/ezurio/bl54l15u_dvk/support/nrf54l15_cpuflpr.JLinkScript

@@ -0,0 +1,5 @@
+int InitTarget(void) {
+  // Base address where DMI registers can be found in the APB address space
+  JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x5004C400");
+  return 0;
+}