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include: arch: riscv: rename global macro

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SR and LR were used as global names for load and store RISC-V assembler
operations, colliding with other uses such as SR for STATUS REGISTER in
some peripherals. Renamed them to a longer more specific name to avoid
the collision.

Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
This commit is contained in:
Karsten Koenig 2019-08-12 23:07:40 +02:00 • committed by Ioannis Glaropoulos
commit f0d4bdfe3f
3 changed files with 160 additions and 160 deletions
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74
arch/riscv/core/swap.S
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@ -26,45 +26,45 @@ SECTION_FUNC(exception.other, __swap)
#ifdef CONFIG_EXECUTION_BENCHMARKING
addi sp, sp, -__z_arch_esf_t_SIZEOF
SR ra, __z_arch_esf_t_ra_OFFSET(sp)
SR gp, __z_arch_esf_t_gp_OFFSET(sp)
SR tp, __z_arch_esf_t_tp_OFFSET(sp)
SR t0, __z_arch_esf_t_t0_OFFSET(sp)
SR t1, __z_arch_esf_t_t1_OFFSET(sp)
SR t2, __z_arch_esf_t_t2_OFFSET(sp)
SR t3, __z_arch_esf_t_t3_OFFSET(sp)
SR t4, __z_arch_esf_t_t4_OFFSET(sp)
SR t5, __z_arch_esf_t_t5_OFFSET(sp)
SR t6, __z_arch_esf_t_t6_OFFSET(sp)
SR a0, __z_arch_esf_t_a0_OFFSET(sp)
SR a1, __z_arch_esf_t_a1_OFFSET(sp)
SR a2, __z_arch_esf_t_a2_OFFSET(sp)
SR a3, __z_arch_esf_t_a3_OFFSET(sp)
SR a4, __z_arch_esf_t_a4_OFFSET(sp)
SR a5, __z_arch_esf_t_a5_OFFSET(sp)
SR a6, __z_arch_esf_t_a6_OFFSET(sp)
SR a7, __z_arch_esf_t_a7_OFFSET(sp)
RV_OP_STOREREG ra, __z_arch_esf_t_ra_OFFSET(sp)
RV_OP_STOREREG gp, __z_arch_esf_t_gp_OFFSET(sp)
RV_OP_STOREREG tp, __z_arch_esf_t_tp_OFFSET(sp)
RV_OP_STOREREG t0, __z_arch_esf_t_t0_OFFSET(sp)
RV_OP_STOREREG t1, __z_arch_esf_t_t1_OFFSET(sp)
RV_OP_STOREREG t2, __z_arch_esf_t_t2_OFFSET(sp)
RV_OP_STOREREG t3, __z_arch_esf_t_t3_OFFSET(sp)
RV_OP_STOREREG t4, __z_arch_esf_t_t4_OFFSET(sp)
RV_OP_STOREREG t5, __z_arch_esf_t_t5_OFFSET(sp)
RV_OP_STOREREG t6, __z_arch_esf_t_t6_OFFSET(sp)
RV_OP_STOREREG a0, __z_arch_esf_t_a0_OFFSET(sp)
RV_OP_STOREREG a1, __z_arch_esf_t_a1_OFFSET(sp)
RV_OP_STOREREG a2, __z_arch_esf_t_a2_OFFSET(sp)
RV_OP_STOREREG a3, __z_arch_esf_t_a3_OFFSET(sp)
RV_OP_STOREREG a4, __z_arch_esf_t_a4_OFFSET(sp)
RV_OP_STOREREG a5, __z_arch_esf_t_a5_OFFSET(sp)
RV_OP_STOREREG a6, __z_arch_esf_t_a6_OFFSET(sp)
RV_OP_STOREREG a7, __z_arch_esf_t_a7_OFFSET(sp)
call read_timer_start_of_swap
LR ra, __z_arch_esf_t_ra_OFFSET(sp)
LR gp, __z_arch_esf_t_gp_OFFSET(sp)
LR tp, __z_arch_esf_t_tp_OFFSET(sp)
LR t0, __z_arch_esf_t_t0_OFFSET(sp)
LR t1, __z_arch_esf_t_t1_OFFSET(sp)
LR t2, __z_arch_esf_t_t2_OFFSET(sp)
LR t3, __z_arch_esf_t_t3_OFFSET(sp)
LR t4, __z_arch_esf_t_t4_OFFSET(sp)
LR t5, __z_arch_esf_t_t5_OFFSET(sp)
LR t6, __z_arch_esf_t_t6_OFFSET(sp)
LR a0, __z_arch_esf_t_a0_OFFSET(sp)
LR a1, __z_arch_esf_t_a1_OFFSET(sp)
LR a2, __z_arch_esf_t_a2_OFFSET(sp)
LR a3, __z_arch_esf_t_a3_OFFSET(sp)
LR a4, __z_arch_esf_t_a4_OFFSET(sp)
LR a5, __z_arch_esf_t_a5_OFFSET(sp)
LR a6, __z_arch_esf_t_a6_OFFSET(sp)
LR a7, __z_arch_esf_t_a7_OFFSET(sp)
RV_OP_LOADREG ra, __z_arch_esf_t_ra_OFFSET(sp)
RV_OP_LOADREG gp, __z_arch_esf_t_gp_OFFSET(sp)
RV_OP_LOADREG tp, __z_arch_esf_t_tp_OFFSET(sp)
RV_OP_LOADREG t0, __z_arch_esf_t_t0_OFFSET(sp)
RV_OP_LOADREG t1, __z_arch_esf_t_t1_OFFSET(sp)
RV_OP_LOADREG t2, __z_arch_esf_t_t2_OFFSET(sp)
RV_OP_LOADREG t3, __z_arch_esf_t_t3_OFFSET(sp)
RV_OP_LOADREG t4, __z_arch_esf_t_t4_OFFSET(sp)
RV_OP_LOADREG t5, __z_arch_esf_t_t5_OFFSET(sp)
RV_OP_LOADREG t6, __z_arch_esf_t_t6_OFFSET(sp)
RV_OP_LOADREG a0, __z_arch_esf_t_a0_OFFSET(sp)
RV_OP_LOADREG a1, __z_arch_esf_t_a1_OFFSET(sp)
RV_OP_LOADREG a2, __z_arch_esf_t_a2_OFFSET(sp)
RV_OP_LOADREG a3, __z_arch_esf_t_a3_OFFSET(sp)
RV_OP_LOADREG a4, __z_arch_esf_t_a4_OFFSET(sp)
RV_OP_LOADREG a5, __z_arch_esf_t_a5_OFFSET(sp)
RV_OP_LOADREG a6, __z_arch_esf_t_a6_OFFSET(sp)
RV_OP_LOADREG a7, __z_arch_esf_t_a7_OFFSET(sp)
/* Release stack space */
addi sp, sp, __z_arch_esf_t_SIZEOF
@ -83,7 +83,7 @@ SECTION_FUNC(exception.other, __swap)
la t0, _kernel
/* Get pointer to _kernel.current */
LR t1, _kernel_offset_to_current(t0)
RV_OP_LOADREG t1, _kernel_offset_to_current(t0)
/* Load return value of __swap function in temp register t2 */
lw t2, _thread_offset_to_swap_return_value(t1)