From f0d21fb49735b65e9035e0f2b4a8eaa12e3bd46a Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Tue, 3 Dec 2024 07:30:39 +0800 Subject: [PATCH] drivers/pinctrl: Enable pinctrl driver for it51xxx series Enable pinctrl driver for ITE it51xxx series. Signed-off-by: Tim Lin --- drivers/pinctrl/pinctrl_ite_it8xxx2.c | 2 +- dts/riscv/ite/it51xxx-pinctrl-map.dtsi | 396 +++++++++++++++++++++++++ dts/riscv/ite/it51xxx.dtsi | 255 ++++++++++++++++ soc/ite/ec/it51xxx/chip_chipregs.h | 5 + 4 files changed, 657 insertions(+), 1 deletion(-) create mode 100644 dts/riscv/ite/it51xxx-pinctrl-map.dtsi diff --git a/drivers/pinctrl/pinctrl_ite_it8xxx2.c b/drivers/pinctrl/pinctrl_ite_it8xxx2.c index 35317edd2ba..1416af04809 100644 --- a/drivers/pinctrl/pinctrl_ite_it8xxx2.c +++ b/drivers/pinctrl/pinctrl_ite_it8xxx2.c @@ -289,7 +289,7 @@ static int pinctrl_kscan_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins) return -EINVAL; } -#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1 +#if defined(CONFIG_SOC_IT8XXX2_REG_SET_V1) || defined(CONFIG_SOC_SERIES_IT51XXX) uint8_t pin_mask = BIT(pins->pin); volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl; diff --git a/dts/riscv/ite/it51xxx-pinctrl-map.dtsi b/dts/riscv/ite/it51xxx-pinctrl-map.dtsi new file mode 100644 index 00000000000..f5bcaf53a23 --- /dev/null +++ b/dts/riscv/ite/it51xxx-pinctrl-map.dtsi @@ -0,0 +1,396 @@ +/* + * Copyright (c) 2025 ITE Corporation. All Rights Reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + /* ADC alternate function */ + adc0_ch0_gpi0_default: adc0_ch0_gpi0_default { + pinmuxs = <&pinctrli 0 IT8XXX2_ALT_FUNC_1>; + }; + + adc0_ch1_gpi1_default: adc0_ch1_gpi1_default { + pinmuxs = <&pinctrli 1 IT8XXX2_ALT_FUNC_1>; + }; + + adc0_ch2_gpi2_default: adc0_ch2_gpi2_default { + pinmuxs = <&pinctrli 2 IT8XXX2_ALT_FUNC_1>; + }; + + adc0_ch3_gpi3_default: adc0_ch3_gpi3_default { + pinmuxs = <&pinctrli 3 IT8XXX2_ALT_FUNC_1>; + }; + + adc0_ch4_gpi4_default: adc0_ch4_gpi4_default { + pinmuxs = <&pinctrli 4 IT8XXX2_ALT_FUNC_1>; + }; + + adc0_ch5_gpi5_default: adc0_ch5_gpi5_default { + pinmuxs = <&pinctrli 5 IT8XXX2_ALT_FUNC_1>; + }; + + adc0_ch6_gpi6_default: adc0_ch6_gpi6_default { + pinmuxs = <&pinctrli 6 IT8XXX2_ALT_FUNC_1>; + }; + + adc0_ch7_gpi7_default: adc0_ch7_gpi7_default { + pinmuxs = <&pinctrli 7 IT8XXX2_ALT_FUNC_1>; + }; + + /* I2C alternate function */ + i2c0_clk_gpf2_default: i2c0_clk_gpf2_default { + pinmuxs = <&pinctrlf 2 IT8XXX2_ALT_FUNC_1>; + }; + + i2c0_data_gpf3_default: i2c0_data_gpf3_default { + pinmuxs = <&pinctrlf 3 IT8XXX2_ALT_FUNC_1>; + }; + + i2c1_clk_gpc1_default: i2c1_clk_gpc1_default { + pinmuxs = <&pinctrlc 1 IT8XXX2_ALT_FUNC_1>; + }; + + i2c1_data_gpc2_default: i2c1_data_gpc2_default { + pinmuxs = <&pinctrlc 2 IT8XXX2_ALT_FUNC_1>; + }; + + i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { + pinmuxs = <&pinctrlf 6 IT8XXX2_ALT_FUNC_1>; + }; + + i2c2_data_gpf7_default: i2c2_data_gpf7_default { + pinmuxs = <&pinctrlf 7 IT8XXX2_ALT_FUNC_1>; + }; + + i2c3_clk_gph1_default: i2c3_clk_gph1_default { + pinmuxs = <&pinctrlh 1 IT8XXX2_ALT_FUNC_4>; + }; + + i2c3_data_gph2_default: i2c3_data_gph2_default { + pinmuxs = <&pinctrlh 2 IT8XXX2_ALT_FUNC_4>; + }; + + i2c4_clk_gpe0_default: i2c4_clk_gpe0_default { + pinmuxs = <&pinctrle 0 IT8XXX2_ALT_FUNC_4>; + }; + + i2c4_data_gpe7_default: i2c4_data_gpe7_default { + pinmuxs = <&pinctrle 7 IT8XXX2_ALT_FUNC_3>; + }; + + i2c5_clk_gpa4_default: i2c5_clk_gpa4_default { + pinmuxs = <&pinctrla 4 IT8XXX2_ALT_FUNC_3>; + }; + + i2c5_data_gpa5_default: i2c5_data_gpa5_default { + pinmuxs = <&pinctrla 5 IT8XXX2_ALT_FUNC_3>; + }; + + i2c6_clk_gpd0_default: i2c6_clk_gpd0_default { + pinmuxs = <&pinctrld 0 IT8XXX2_ALT_FUNC_3>; + }; + + i2c6_data_gpd1_default: i2c6_data_gpd1_default { + pinmuxs = <&pinctrld 1 IT8XXX2_ALT_FUNC_3>; + }; + + i2c7_clk_gpb2_default: i2c7_clk_gpb2_default { + pinmuxs = <&pinctrlb 2 IT8XXX2_ALT_FUNC_4>; + }; + + i2c7_data_gph0_default: i2c7_data_gph0_default { + pinmuxs = <&pinctrlh 0 IT8XXX2_ALT_FUNC_4>; + }; + + i2c8_clk_gpb5_default: i2c8_clk_gpb5_default { + pinmuxs = <&pinctrlb 5 IT8XXX2_ALT_FUNC_4>; + }; + + i2c8_data_gpj6_default: i2c8_data_gpj6_default { + pinmuxs = <&pinctrlj 6 IT8XXX2_ALT_FUNC_4>; + }; + + /* I3C alternate function */ + i3c0_clk_gpj3_default: i3c0_clk_gpj3_default { + pinmuxs = <&pinctrlj 3 IT8XXX2_ALT_FUNC_1>; + }; + + i3c0_data_gpj4_default: i3c0_data_gpj4_default { + pinmuxs = <&pinctrlj 4 IT8XXX2_ALT_FUNC_1>; + }; + + i3c1_clk_gpj5_default: i3c1_clk_gpj5_default { + pinmuxs = <&pinctrlj 5 IT8XXX2_ALT_FUNC_1>; + }; + + i3c1_data_gpe1_default: i3c1_data_gpe1_default { + pinmuxs = <&pinctrle 1 IT8XXX2_ALT_FUNC_1>; + }; + + i3c2_clk_gpe2_default: i3c2_clk_gpe2_default { + pinmuxs = <&pinctrle 2 IT8XXX2_ALT_FUNC_1>; + }; + + i3c2_data_gpe3_default: i3c2_data_gpe3_default { + pinmuxs = <&pinctrle 3 IT8XXX2_ALT_FUNC_1>; + }; + + i3c3_clk_gpf0_default: i3c3_clk_gpf0_default { + pinmuxs = <&pinctrlf 0 IT8XXX2_ALT_FUNC_1>; + }; + + i3c3_data_gpf1_default: i3c3_data_gpf1_default { + pinmuxs = <&pinctrlf 1 IT8XXX2_ALT_FUNC_1>; + }; + + /* Keyboard alternate function */ + kso0_default: kso0_gpk0_default: kso0_gpk0_default { + pinmuxs = <&pinctrlk 0 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso1_default: kso1_gpk1_default: kso1_gpk1_default { + pinmuxs = <&pinctrlk 1 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso2_default: kso2_gpk2_default: kso2_gpk2_default { + pinmuxs = <&pinctrlk 2 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso3_default: kso3_gpk3_default: kso3_gpk3_default { + pinmuxs = <&pinctrlk 3 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso4_default: kso4_gpk4_default: kso4_gpk4_default { + pinmuxs = <&pinctrlk 4 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso5_default: kso5_gpk5_default: kso5_gpk5_default { + pinmuxs = <&pinctrlk 5 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso6_default: kso6_gpk6_default: kso6_gpk6_default { + pinmuxs = <&pinctrlk 6 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso7_default: kso7_gpk7_default: kso7_gpk7_default { + pinmuxs = <&pinctrlk 7 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso8_default: kso8_gpl0_default: kso8_gpl0_default { + pinmuxs = <&pinctrll 0 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso9_default: kso9_gpl1_default: kso9_gpl1_default { + pinmuxs = <&pinctrll 1 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso10_default: kso10_gpl2_default: kso10_gpl2_default { + pinmuxs = <&pinctrll 2 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso11_default: kso11_gpl3_default: kso11_gpl3_default { + pinmuxs = <&pinctrll 3 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso12_default: kso12_gpl4_default: kso12_gpl4_default { + pinmuxs = <&pinctrll 4 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso13_default: kso13_gpl5_default: kso13_gpl5_default { + pinmuxs = <&pinctrll 5 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso14_default: kso14_gpl6_default: kso14_gpl6_default { + pinmuxs = <&pinctrll 6 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso15_default: kso15_gpl7_default: kso15_gpl7_default { + pinmuxs = <&pinctrll 7 IT8XXX2_ALT_FUNC_1>; + drive-open-drain; + bias-pull-up; + }; + + kso16_default: kso16_gpc3_default: kso16_gpc3_default { + pinmuxs = <&pinctrlc 3 IT8XXX2_ALT_FUNC_1>; + bias-pull-up; + }; + + kso17_default: kso17_gpc5_default: kso17_gpc5_default { + pinmuxs = <&pinctrlc 5 IT8XXX2_ALT_FUNC_1>; + bias-pull-up; + }; + + ksi0_default: ksi0_gpn0_default: ksi0_gpn0_default { + pinmuxs = <&pinctrln 0 IT8XXX2_ALT_FUNC_1>; + bias-pull-up; + }; + + ksi1_default: ksi1_gpn1_default: ksi1_gpn1_default { + pinmuxs = <&pinctrln 1 IT8XXX2_ALT_FUNC_1>; + bias-pull-up; + }; + + ksi2_default: ksi2_gpn2_default: ksi2_gpn2_default { + pinmuxs = <&pinctrln 2 IT8XXX2_ALT_FUNC_1>; + bias-pull-up; + }; + + ksi3_default: ksi3_gpn3_default: ksi3_gpn3_default { + pinmuxs = <&pinctrln 3 IT8XXX2_ALT_FUNC_1>; + bias-pull-up; + }; + + ksi4_default: ksi4_gpn4_default: ksi4_gpn4_default { + pinmuxs = <&pinctrln 4 IT8XXX2_ALT_FUNC_1>; + bias-pull-up; + }; + + ksi5_default: ksi5_gpn5_default: ksi5_gpn5_default { + pinmuxs = <&pinctrln 5 IT8XXX2_ALT_FUNC_1>; + bias-pull-up; + }; + + ksi6_default: ksi6_gpn6_default: ksi6_gpn6_default { + pinmuxs = <&pinctrln 6 IT8XXX2_ALT_FUNC_1>; + bias-pull-up; + }; + + ksi7_default: ksi7_gpn7_default: ksi7_gpn7_default { + pinmuxs = <&pinctrln 7 IT8XXX2_ALT_FUNC_1>; + bias-pull-up; + }; + + /* PECI alternate function */ + peci_gpf6_default: peci_gpf6_default { + pinmuxs = <&pinctrlf 6 IT8XXX2_ALT_FUNC_3>; + }; + + /* PWM alternate function */ + pwm0_gpa0_default: pwm0_gpa0_default { + pinmuxs = <&pinctrla 0 IT8XXX2_ALT_FUNC_1>; + }; + + pwm1_gpa1_default: pwm1_gpa1_default { + pinmuxs = <&pinctrla 1 IT8XXX2_ALT_FUNC_1>; + }; + + pwm2_gpa2_default: pwm2_gpa2_default { + pinmuxs = <&pinctrla 2 IT8XXX2_ALT_FUNC_1>; + }; + + pwm3_gpa3_default: pwm3_gpa3_default { + pinmuxs = <&pinctrla 3 IT8XXX2_ALT_FUNC_1>; + }; + + pwm4_gpa4_default: pwm4_gpa4_default { + pinmuxs = <&pinctrla 4 IT8XXX2_ALT_FUNC_1>; + }; + + pwm5_gpa5_default: pwm5_gpa5_default { + pinmuxs = <&pinctrla 5 IT8XXX2_ALT_FUNC_1>; + }; + + pwm6_gpa6_default: pwm6_gpa6_default { + pinmuxs = <&pinctrla 6 IT8XXX2_ALT_FUNC_1>; + }; + + pwm7_gpa7_default: pwm7_gpa7_default { + pinmuxs = <&pinctrla 7 IT8XXX2_ALT_FUNC_1>; + }; + + /* SSPI alternate function */ + ssce0_gpj7_default: ssce0_gpj7_default { + pinmuxs = <&pinctrlj 7 IT8XXX2_ALT_FUNC_4>; + }; + + ssce1_gph7_default: ssce1_gph7_default { + pinmuxs = <&pinctrlh 7 IT8XXX2_ALT_FUNC_3>; + }; + + ssck_gpa6_default: ssck_gpa6_default { + pinmuxs = <&pinctrla 6 IT8XXX2_ALT_FUNC_3>; + }; + + smosi_gpc6_default: smosi_gpc6_default { + pinmuxs = <&pinctrlc 6 IT8XXX2_ALT_FUNC_3>; + }; + + smiso_gpc4_default: smiso_gpc4_default { + pinmuxs = <&pinctrlc 4 IT8XXX2_ALT_FUNC_3>; + }; + + /* Tachometer alternate function */ + tach0a_gpd6_default: tach0a_gpd6_default { + pinmuxs = <&pinctrld 6 IT8XXX2_ALT_FUNC_1>; + }; + + tach1a_gpd7_default: tach1a_gpd7_default { + pinmuxs = <&pinctrld 7 IT8XXX2_ALT_FUNC_1>; + }; + + tach2a_gpj0_default: tach2a_gpj0_default { + pinmuxs = <&pinctrlj 0 IT8XXX2_ALT_FUNC_3>; + }; + + tach0b_gpc6_default: tach0b_gpc6_default { + pinmuxs = <&pinctrlc 6 IT8XXX2_ALT_FUNC_4>; + }; + + tach1b_gpj6_default: tach1b_gpj6_default { + pinmuxs = <&pinctrlj 6 IT8XXX2_ALT_FUNC_3>; + }; + + tach2b_gpj1_default: tach2b_gpj1_default { + pinmuxs = <&pinctrlj 1 IT8XXX2_ALT_FUNC_3>; + }; + + /* UART alternate function */ + uart1_rx_gpc7_default: uart1_rx_gpc7_default { + pinmuxs = <&pinctrlc 7 IT8XXX2_ALT_FUNC_4>; + }; + + uart1_tx_gpe6_default: uart1_tx_gpe6_default { + pinmuxs = <&pinctrle 6 IT8XXX2_ALT_FUNC_4>; + }; + + uart2_rx_gph1_default: uart2_rx_gph1_default { + pinmuxs = <&pinctrlh 1 IT8XXX2_ALT_FUNC_3>; + }; + + uart2_tx_gph2_default: uart2_tx_gph2_default { + pinmuxs = <&pinctrlh 2 IT8XXX2_ALT_FUNC_3>; + }; +}; diff --git a/dts/riscv/ite/it51xxx.dtsi b/dts/riscv/ite/it51xxx.dtsi index 722a721742b..7379eab7af3 100644 --- a/dts/riscv/ite/it51xxx.dtsi +++ b/dts/riscv/ite/it51xxx.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -65,6 +66,260 @@ reg = <0x00f01600 0x100>; }; + pinctrl: pin-controller { + compatible = "ite,it8xxx2-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + }; + + pinctrla: pinctrl@f01610 { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01610 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + BIT(5) BIT(5) BIT(4) BIT(3) >; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0 >; + volt-sel = <0xf016d4 0xf016d4 0xf016d4 0xf016d4 + NO_FUNC NO_FUNC 0xf016d4 0xf016d4>; + volt-sel-mask = ; + #pinmux-cells = <2>; + gpio-group; + }; + + pinctrlb: pinctrl@f01618 { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01618 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 BIT(1) 0 + 0 BIT(5) 0 0 >; + func4-gcr = ; + func4-en-mask = <0 0 BIT(2) 0 + 0 BIT(3) 0 0 >; + volt-sel = ; + volt-sel-mask = <0 0 BIT(2) 0 + 0 0 0 0 >; + #pinmux-cells = <2>; + gpio-group; + }; + + pinctrlc: pinctrl@f01620 { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01620 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + BIT(4) 0 BIT(4) BIT(7) >; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 BIT(0) BIT(0) >; + volt-sel = <0xf016d6 NO_FUNC NO_FUNC 0xf016d6 + 0xf016d6 0xf016d6 0xf016d6 NO_FUNC >; + volt-sel-mask = ; + #pinmux-cells = <2>; + gpio-group; + }; + + pinctrld: pinctrl@f01628 { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01628 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016ed 0xf016ed NO_FUNC NO_FUNC + 0xf03292 0xf016f0 NO_FUNC NO_FUNC >; + func3-en-mask = ; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0 >; + volt-sel = ; + volt-sel-mask = <0 0 0 0 + 0 BIT(5) BIT(6) BIT(7) >; + #pinmux-cells = <2>; + gpio-group; + }; + + pinctrle: pinctrl@f01630 { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01630 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016f3 NO_FUNC NO_FUNC NO_FUNC + NO_FUNC 0xf016f0 0xf016fe 0xf016fe>; + func3-en-mask = ; + func4-gcr = <0xf016fe NO_FUNC NO_FUNC NO_FUNC + NO_FUNC NO_FUNC 0xf016f5 NO_FUNC >; + func4-en-mask = ; + volt-sel = ; + volt-sel-mask = <0 BIT(1) BIT(2) BIT(3) + 0 BIT(5) 0 0 >; + #pinmux-cells = <2>; + gpio-group; + }; + + pinctrlf: pinctrl@f01638 { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01638 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0 BIT(4) 0 >; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0 >; + volt-sel = <0xf016d9 0xf016d9 NO_FUNC NO_FUNC + NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; + volt-sel-mask = ; + #pinmux-cells = <2>; + gpio-group; + }; + + pinctrlg: pinctrl@f01640 { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01640 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 BIT(3) 0 0 + 0 0 BIT(1) 0 >; + func4-gcr = ; + func4-en-mask = <0 BIT(6) 0 0 + 0 0 0 0 >; + volt-sel = <0xf016da NO_FUNC 0xf016da NO_FUNC + NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; + volt-sel-mask = ; + #pinmux-cells = <2>; + gpio-group; + }; + + pinctrlh: pinctrl@f01648 { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01648 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016f0 0xf016f5 0xf016f5 0xf016f0 + 0xf016f0 NO_FUNC NO_FUNC 0xf016f0>; + func3-en-mask = ; + func4-gcr = <0xf016ed 0xf016f1 0xf016f1 NO_FUNC + NO_FUNC NO_FUNC NO_FUNC 0xf016f5>; + func4-en-mask = ; + volt-sel = ; + volt-sel-mask = <0 0 0 BIT(3) + BIT(4) BIT(5) BIT(6) BIT(7) >; + #pinmux-cells = <2>; + gpio-group; + }; + + pinctrli: pinctrl@f01650 { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01650 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 BIT(3) BIT(3) BIT(3) >; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0 >; + volt-sel = <0xf016dc 0xf016dc 0xf016dc 0xf016dc + 0xf016dc 0xf016dc 0xf016dc 0xf016dc>; + volt-sel-mask = ; + #pinmux-cells = <2>; + gpio-group; + }; + + pinctrlj: pinctrl@f01658 { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01658 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016f1 0xf016fe NO_FUNC NO_FUNC + NO_FUNC NO_FUNC 0xf016f4 0xf016d1>; + func3-en-mask = ; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 BIT(3) BIT(4) >; + volt-sel = <0xf016dd NO_FUNC 0xf016dd 0xf016dd + 0xf016dd 0xf016dd 0xf016dd 0xf016dd>; + volt-sel-mask = ; + #pinmux-cells = <2>; + gpio-group; + }; + + pinctrlk: pinctrl@f01d2d { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01d2d 1 /* KSOLGCTRL */ + 0x00f01d02 1>; /* KSOCTRL */ + pp-od-mask = ; + pullup-mask = ; + #pinmux-cells = <2>; + }; + + pinctrll: pinctrl@f01d2e { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01d2e 1 /* KSOHGCTRL */ + 0x00f01d02 1>; /* KSOCTRL */ + pp-od-mask = ; + pullup-mask = ; + #pinmux-cells = <2>; + }; + + pinctrlm: pinctrl@f016a0 { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f016a0 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0 0 0 >; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0 >; + volt-sel = ; + volt-sel-mask = <0 0 0 0 + 0 0 0 0 >; + #pinmux-cells = <2>; + gpio-group; + }; + + pinctrln: pinctrl@f01d2c { + compatible = "ite,it8xxx2-pinctrl-func"; + reg = <0x00f01d2c 1 /* KSIGCTRL */ + 0x00f01d05 1>; /* KSICTRL */ + pp-od-mask = ; + pullup-mask = ; + #pinmux-cells = <2>; + }; + wuc1: wakeup-controller@f01b00 { compatible = "ite,it51xxx-wuc"; reg = <0x00f01b00 1 /* WUEMR1 */ diff --git a/soc/ite/ec/it51xxx/chip_chipregs.h b/soc/ite/ec/it51xxx/chip_chipregs.h index 8ad65446753..7111de3f166 100644 --- a/soc/ite/ec/it51xxx/chip_chipregs.h +++ b/soc/ite/ec/it51xxx/chip_chipregs.h @@ -183,6 +183,7 @@ struct gpio_it51xxx_regs { /* GPIO register fields */ /* 0x00: General Control */ #define IT51XXX_GPIO_LPCRSTEN (BIT(2) | BIT(1)) +#define ITE_EC_GPIO_LPCRSTEN IT51XXX_GPIO_LPCRSTEN #define IT51XXX_GPIO_GCR_ESPI_RST_D2 0x2 #define IT51XXX_GPIO_GCR_ESPI_RST_POS 1 #define IT51XXX_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT51XXX_GPIO_GCR_ESPI_RST_POS) @@ -298,4 +299,8 @@ struct gctrl_it51xxx_regs { /* 0x38: Special Control 9 */ #define IT51XXX_GCTRL_ALTIE BIT(4) +/* Alias gpio_ite_ec_regs to gpio_it51xxx_regs for compatibility */ +#define gpio_ite_ec_regs gpio_it51xxx_regs +#define GPIO_ITE_EC_REGS_BASE GPIO_IT51XXX_REGS_BASE + #endif /* CHIP_CHIPREGS_H */