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soc: nxp: k8x: move clk divider options to device tree

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Use kinetis SIM clock divider options set in device tree
instead of kconfig

Signed-off-by: Mikkel Jakobsen <mikkel.aunsbjerg@prevas.dk>
This commit is contained in:
Mikkel Jakobsen 2021-03-04 18:05:49 +01:00 • committed by Maureen Helm
commit f0c01561fe
3 changed files with 38 additions and 32 deletions
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28
dts/arm/nxp/nxp_k8x.dtsi
View file

@ -43,6 +43,34 @@
reg = <0x40047000 0x2000>;
label = "SIM";
#clock-cells = <3>;
core_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <1>;
#clock-cells = <0>;
};
bus_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <2>;
#clock-cells = <0>;
};
flexbus_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <2>;
#clock-cells = <0>;
};
flash_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <5>;
#clock-cells = <0>;
};
};
mcg: clock-controller@40064000 {

28
soc/arm/nxp_kinetis/k8x/Kconfig.soc
View file

@ -41,32 +41,4 @@ config SOC_PART_NUMBER_KINETIS_K8X
number selection choice defines the default value for this
string.
config K8X_CORE_CLOCK_DIVIDER
int "Freescale K8x core clock divider"
default 1
help
This option specifies the divide value for the K8x processor core clock
from the system clock.
config K8X_BUS_CLOCK_DIVIDER
int "Freescale K8x bus clock divider"
default 2
help
This option specifies the divide value for the K8x bus clock from the
system clock.
config K8X_FLEXBUS_CLOCK_DIVIDER
int "Freescale K8x FlexBus clock divider"
default 2
help
This option specifies the divide value for the K8x FlexBus clock from the
system clock.
config K8X_FLASH_CLOCK_DIVIDER
int "Freescale K8x flash clock divider"
default 5
help
This option specifies the divide value for the K8x flash clock from the
system clock.
endif # SOC_SERIES_KINETIS_K8X

14
soc/arm/nxp_kinetis/k8x/soc.c
View file

@ -22,6 +22,12 @@
#define RUNM_VLPR (2)
#define RUNM_HSRUN (3)
#define CLOCK_NODEID(clk) \
DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
#define CLOCK_DIVIDER(clk) \
DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
static const osc_config_t osc_config = {
.freq = CONFIG_OSC_XTAL0_FREQ,
.capLoad = 0,
@ -54,10 +60,10 @@ static const mcg_pll_config_t pll0_config = {
static const sim_clock_config_t sim_config = {
.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_K8X_CORE_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV2(CONFIG_K8X_BUS_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV3(CONFIG_K8X_FLEXBUS_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV4(CONFIG_K8X_FLASH_CLOCK_DIVIDER - 1),
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
/* Divide PLL output frequency by 2 for peripherals */
.pllFllDiv = (1),
.pllFllFrac = (0),