michaelh/zephyr
1
0
Fork 0
Code Releases Activity

arch: arm: cortex_r: linker.ld: Clean-up

Browse source 
This commit cleans up the linker.ld file for the Cortex-R arch.

* Convert all TAB characters to SPACE.
* Fix insane placement of curly brackets.
* Fix overall text alignments.
* Remove the special handlings for the Cortex-M devices that were
  copied from `include/arm/aarch32/cortex_m/scripts/linker.ld`.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2020-02-10 14:20:07 +09:00 • committed by Ioannis Glaropoulos
commit f053f1b25d
1 changed files with 129 additions and 166 deletions
Download patch file Download diff file Expand all files Collapse all files

37
include/arch/arm/aarch32/cortex_r/scripts/linker.ld
View file

@ -33,28 +33,17 @@
#define _DATA_IN_ROM
#endif
#if !defined(SKIP_TO_KINETIS_FLASH_CONFIG)
#define SKIP_TO_KINETIS_FLASH_CONFIG
#endif
#if !defined(CONFIG_XIP) && (CONFIG_FLASH_SIZE == 0)
#define ROM_ADDR RAM_ADDR
#else
#define ROM_ADDR (CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET)
#endif
#ifdef CONFIG_HAS_TI_CCFG
#define CCFG_SIZE 88
#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET - \
CCFG_SIZE)
#define CCFG_ADDR (ROM_ADDR + ROM_SIZE)
#else
#if CONFIG_FLASH_LOAD_SIZE > 0
#define ROM_SIZE CONFIG_FLASH_LOAD_SIZE
#else
#define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)
#endif
#endif
#if defined(CONFIG_XIP)
#if defined(CONFIG_IS_BOOTLOADER)
@ -92,17 +81,10 @@ _region_min_align = 4;
MEMORY
{
FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
#ifdef CONFIG_HAS_TI_CCFG
FLASH_CCFG (rwx): ORIGIN = CCFG_ADDR, LENGTH = CCFG_SIZE
#endif
#ifdef DT_CCM_BASE_ADDRESS
CCM (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K
#endif
SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
#ifdef CONFIG_BT_STM32_IPM
SRAM1 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE
SRAM2 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE
#endif
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K
}
@ -111,7 +93,6 @@ ENTRY(CONFIG_KERNEL_ENTRY)
SECTIONS
{
#include <linker/rel-sections.ld>
/*
@ -241,14 +222,6 @@ SECTIONS
GROUP_END(ROMABLE_REGION)
/* Some TI SoCs have a special configuration footer, at the end of flash. */
#ifdef CONFIG_HAS_TI_CCFG
SECTION_PROLOGUE(.ti_ccfg,,)
{
KEEP(*(TI_CCFG))
} > FLASH_CCFG
#endif
/*
* These are here according to 'arm-zephyr-elf-ld --verbose',
* before data section.
@ -270,16 +243,6 @@ SECTIONS
. = ALIGN(_region_min_align);
_image_ram_start = .;
#if defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_IS_BOOTLOADER)
/* Must be first in ramable region */
SECTION_PROLOGUE(.st_stm32f0x_vt,(NOLOAD),)
{
_ram_vector_start = .;
. += _vector_end - _vector_start;
_ram_vector_end = .;
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
#endif
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/