From f003c8b50845f269727b631b9bc4d8d4bf7316db Mon Sep 17 00:00:00 2001 From: Ioannis Glaropoulos Date: Mon, 9 Mar 2020 20:44:44 +0100 Subject: [PATCH] tests: arch: arm: interrupt: test the spurious ISR handler We extend the interrupt test for ARM Cortex-M so that it can test the behavior of the spurious ISR handler. Signed-off-by: Ioannis Glaropoulos --- tests/arch/arm/arm_interrupt/README.txt | 3 ++- .../arch/arm/arm_interrupt/src/arm_interrupt.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/tests/arch/arm/arm_interrupt/README.txt b/tests/arch/arm/arm_interrupt/README.txt index 7cb8c736f88..011ff006df4 100644 --- a/tests/arch/arm/arm_interrupt/README.txt +++ b/tests/arch/arm/arm_interrupt/README.txt @@ -6,7 +6,8 @@ Description: The first test verifies that we can handle system fault conditions while running in handler mode (i.e. in an ISR). Only for ARM -Cortex-M targets. +Cortex-M targets. The test also verifies the behavior of the +spurious interrupt handler. The second test verifies that threads in user mode, despite being able to call the irq_lock() and irq_unlock() functions without triggering a CPU fault, diff --git a/tests/arch/arm/arm_interrupt/src/arm_interrupt.c b/tests/arch/arm/arm_interrupt/src/arm_interrupt.c index b96db8a4696..187ea4b7d92 100644 --- a/tests/arch/arm/arm_interrupt/src/arm_interrupt.c +++ b/tests/arch/arm/arm_interrupt/src/arm_interrupt.c @@ -87,6 +87,24 @@ void test_arm_interrupt(void) TC_PRINT("Available IRQ line: %u\n", i); + /* Verify that triggering an interrupt in an IRQ line, + * on which an ISR has not yet been installed, leads + * to a fault of type K_ERR_SPURIOUS_IRQ. + */ + expected_reason = K_ERR_SPURIOUS_IRQ; + NVIC_ClearPendingIRQ(i); + NVIC_EnableIRQ(i); + NVIC_SetPendingIRQ(i); + __DSB(); + __ISB(); + + /* Verify that the spurious ISR has led to the fault and the + * expected reason variable is reset. + */ + zassert_true(expected_reason == -1, + "expected_reason has not been reset\n"); + NVIC_DisableIRQ(i); + arch_irq_connect_dynamic(i, 0 /* highest priority */, arm_isr_handler, NULL,